All The Claims

1. A chip-size double side connection package configured such that a semiconductor chip including a semiconductor substrate on which an LSI region and electrode connection regions are formed is connected to wiring for external connection provided on a first main face and to wiring for external connection provided on a second main face, the first and second main faces being located above and below the semiconductor chip, respectively, the chip-size double side connection package comprising:
a low resistance metal charged into holes formed in the electrode connection regions to form through electrodes;
a wiring-added post electrode component which includes post electrodes and front face wiring traces connected to the post electrodes fixed to and electrically connected to upper surface regions of the through electrodes or the electrode connection regions;
a resin between the semiconductor chip and the front face wiring traces; and
tip ends on the second main face of the through electrodes configured for use as the wiring for external connection.
2. The chip-size double side connection package according to claim 1, wherein external electrodes for external connection are formed on the front face wiring traces so as to be connected thereto.
3. (canceled)
4. The chip-size double side connection package according to claim 1, wherein, on the second main face side, a back face insulation layer is applied to the semiconductor substrate such that the tip ends of the through electrodes are exposed, and back face wiring traces to be connected to the tip ends of the through electrodes are formed.
5. The chip-size double side connection package according to claim 4, wherein, on the second main face side, external electrodes to be connected to the back face wiring traces are formed.
6. The chip-size double side connection package according to claim 1, wherein, after the holes corresponding to the through electrodes are formed in the semiconductor substrate, an insulation film is deposited on the wall surfaces of the holes.
7-9. (canceled)
10. A method for manufacturing a chip-size double side connection package configured such that a semiconductor chip including a semiconductor substrate on which an LSI region and electrode connection regions are formed is connected to wiring for external connection provided on a first main face and to wiring for external connection provided on a second main face, the first and second main faces being located above and below the semiconductor chip, respectively, the method being characterized by comprising:
forming a wiring-added post electrode component which includes post electrodes supported by a support portion and front face wiring traces connected to the post electrodes;
forming holes corresponding to through electrodes in the semiconductor substrate at or in the vicinity of the centers of the electrode connection regions to which the through electrodes are to be connected;
charging a low resistance metal into the holes to thereby form the through electrodes;
simultaneously fixing and electrically connecting the plurality of post electrodes of the wiring-added post electrode component, which are coupled together by the support portion, to upper surface regions of the through electrodes or the electrode connection regions;
on the first main face side, charging resin into a space between the semiconductor chip and the support portion, and then separating the support portion so as to expose the front face wiring traces; and
on the second main face side, grinding the semiconductor substrate to form a ground semiconductor substrate so as to expose tip ends of the through electrodes,
wherein the front face wiring traces exposed to the first main face side and the tip ends of the through electrodes exposed to the second main face side are used as the wiring for external connection.
11. The method for manufacturing the chip-size double side connection package according to claim 10, wherein external electrodes for external connection are formed on the front face wiring traces so as to be connected thereto.
12. The method for manufacturing the chip-size double side connection package according to claim 10, wherein, on the second main face side, a back face insulation layer is applied to the ground semiconductor substrate such that the tip ends of the through electrodes are exposed, and external electrodes to be connected to the tip ends of the through electrodes are formed.
13. The method for manufacturing the chip-size double side connection package according to claim 10, wherein, on the second main face side, a back face insulation layer is applied to the ground semiconductor substrate such that the tip ends of the through electrodes are exposed, and back face wiring traces to be connected to the tip ends of the through electrodes are formed.
14. The method for manufacturing the chip-size double side connection package according to claim 13, wherein, on the second main face side, external electrodes to be connected to the back face wiring traces are formed.
15. The method for manufacturing the chip-size double side connection package according to claim 10, wherein, after the holes corresponding to the through electrodes are formed in the semiconductor substrate, an insulation film is deposited on the wall surfaces of the holes.
16. The method for manufacturing the chip-size double side connection package according to claim 10, wherein the wiring-added post electrode component is fabricated such that columnar post electrodes with wiring are grown on an electrically conductive material, which serves as the support portion, to thereby form wiring-added post electrodes integrated with the support portion.
17. The method for manufacturing the chip-size double side connection package according to claim 10, wherein the wiring-added post electrode component is fabricated such that columnar post electrodes with wiring are grown on an insulation tape of thin film applied to one entire surface of the support portion, to thereby form wiring-added post electrodes integrated with the support portion.
18. The method for manufacturing the chip-size double side connection package according to claim 17, wherein, on the first main face side, the insulation tape left after separation of the support portion is used as a protection film.
19. (canceled)

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A capacitive sensor array, comprising:
a plurality of large sensor electrodes located within an active sensing region;
a plurality of small sensor electrodes including a first set of at least four small sensor electrodes and a second set of at least four small sensor electrodes located within the active sensing region, wherein the plurality of large sensor electrodes and the plurality of small sensor electrodes are formed from a single layer of conductive material; and
a plurality of pads located within an edge region bordering the active sensing region,
wherein each small sensor electrode of the first set of small sensor electrodes is electrically connected by a first conductive path through a first set of connecting traces to a first pad of the plurality of pads, wherein a first axis crosses two or more of the small sensor electrodes of the first set of small sensor electrodes, wherein each small sensor electrode of the first set of small sensor electrodes is located on an opposite lateral side of one of the plurality of large sensor electrodes from another small sensor electrode of the first set of small sensor electrodes,
wherein each small sensor electrode of the second set of small sensor electrodes is electrically connected by a conductive path through a second set of connecting traces to a second pad of the plurality of pads, wherein the first conductive path is non-overlapping with the second conductive path, wherein a second axis crosses two or more of the small sensor electrodes of the second set of small sensor electrodes, wherein each small sensor electrode of the second set of small sensor electrodes is located on an opposite lateral side of one of the plurality of large sensor electrodes from another small sensor electrode of the second set of small sensor electrodes.
2. The capacitive sensor array of claim 1, wherein a conductive path through the first set of connecting traces and the first set of small sensor electrodes passes through the edge region and a routing region bordering the active sensing region on an opposite side of the active sensing region from the edge region.
3. The capacitive sensor array of claim 1, wherein for each small sensor electrode of the plurality of sensor electrodes, a shortest line segment between a geometric center of the small sensor electrode and a central longitudinal axis of a large sensor electrode nearest to the geometric center crosses a ground trace and does not cross any other small electrode.
4. The capacitive sensor array of claim 1, wherein the first pad is connected at opposite ends of the first pad to two connecting traces of the first set of connecting traces, and wherein the second pad is connected at opposite ends of the second pad to two connecting traces of the second set of connecting traces.
5. The capacitive sensor array of claim 1, wherein the plurality of pads comprises a pad for each large sensor electrode of the plurality of large sensor electrodes and for each of a plurality of sets of small sensor electrodes, wherein each small sensor electrode in the plurality of sets of small sensor electrodes is electrically connected to every other small sensor electrode in the same set of small sensor electrodes by a set of connecting traces, and wherein the plurality of sets of small sensor electrodes comprises the first set of sensor electrodes and the second set of sensor electrodes.
6. The capacitive sensor array of claim 5, further comprising one or more ground traces in the active sensing region, wherein a number of pads in the edge region is less than or equal to one pad for each large sensor electrode of the plurality of sensor electrodes, for each set of small sensor electrodes of the plurality of small sensor electrodes, and for each of the one or more ground traces.
7. The capacitive sensor array of claim 1, wherein a third axis perpendicular to the first axis and the second axis crosses at least one of the first set of small sensor electrodes and at least one of the second set of small sensor electrodes.
8. The capacitive sensor array of claim 7, wherein a fourth axis parallel to the third axis crosses two or more of the plurality of large sensor electrodes.
9. The capacitive sensor array of claim 8, further comprising one or more additional sets of small sensor electrodes, wherein each small sensor electrode in the one or more additional sets of small sensor electrodes is electrically coupled to every other small sensor electrode in the same set of small sensor electrodes by a set of connecting traces, wherein for each of the two or more large sensor electrodes crossed by the fourth axis, the third axis crosses one small sensor electrode from each of the additional sets of small sensor electrodes.
10. A capacitive sensor array, comprising:
a plurality of large sensor electrodes located within an active sensing region;
a plurality of small sensor electrodes including a first set of small sensor electrodes and a second set of small sensor electrodes located within the active sensing region, wherein the plurality of large sensor electrodes and the plurality of small sensor electrodes are formed from a single layer of conductive material; and
a plurality of pads located within an edge region bordering the active sensing region,
wherein a first conductive path through each of the first set of small electrodes extends from a first pad of the plurality of pads to a routing region opposite the edge region and extends from the routing region to the edge region, wherein a first axis crosses two or more of the small sensor electrodes of the first set of small sensor electrodes, wherein each small sensor electrode of the first set of small sensor electrodes is located on an opposite lateral side of one of the plurality of large sensor electrodes from another small sensor electrode of the first set of small sensor electrodes,
wherein a second conductive path through each of the second set of small electrodes is non-overlapping with the first conductive path and extends from a second pad of the plurality of pads to a routing region opposite the edge region and extends from the routing region to the edge region, wherein a second axis crosses two or more of the small sensor electrodes of the second set of small sensor electrodes, wherein each small sensor electrode of the second set of small sensor electrodes is located on an opposite lateral side of one of the plurality of large sensor electrodes from another small sensor electrode of the second set of small sensor electrodes.
11. The capacitive sensor array of claim 10, wherein for each small sensor electrode of the plurality of sensor electrodes, a shortest line segment between a geometric center of the small sensor electrode and a central longitudinal axis of a large sensor electrode nearest to the geometric center crosses a ground trace and does not cross any other small electrode.
12. The capacitive sensor array of claim 10, wherein the first pad is connected at opposite ends of the first pad to two connecting traces of the first set of connecting traces, and wherein the second pad is connected at opposite ends of the second pad to two connecting traces of the second set of connecting traces.
13. The capacitive sensor array of claim 10, wherein the plurality of pads comprises a pad for each large sensor electrode of the plurality of large sensor electrodes and for each of a plurality of sets of small sensor electrodes, wherein each small sensor electrode in the plurality of sets of small sensor electrodes is electrically connected to every other small sensor electrode in the same set of small sensor electrodes by a set of connecting traces, and wherein the plurality of sets of small sensor electrodes comprises the first set of sensor electrodes and the second set of sensor electrodes.
14. The capacitive sensor array of claim 10, further comprising a plurality of sets of small sensor electrodes, wherein the plurality of sets of small sensor electrodes comprises the first set of small sensor electrodes and the second set of small sensor electrodes, wherein each small sensor electrode in the plurality of sets of small sensor electrodes is electrically coupled to every other small sensor electrode in the same set of small sensor electrodes by a set of connecting traces, wherein a third axis perpendicular to the first axis and the second axis crosses two or more of the plurality of large sensor electrodes, wherein for each of the two or more large sensor electrodes crossed by the third axis, a fourth axis parallel to the third axis crosses one small sensor electrode from each of the plurality of sets of small sensor electrodes.
15. A method, comprising:
providing a plurality of large sensor electrodes located within an active sensing region;
providing a plurality of small sensor electrodes including a first set of at least four small sensor electrodes and a second set of at least four small sensor electrodes located within the active sensing region, wherein the plurality of large sensor electrodes and the plurality of small sensor electrodes are formed from a single layer of conductive material; and
providing a plurality of pads coupled with the capacitance sensor and located within an edge region bordering the active sensing region;
wherein each small sensor electrode of the first set of small sensor electrodes is electrically connected by a first conductive path through a first set of connecting traces to a first pad of the plurality of pads, wherein a first axis crosses two or more of the small sensor electrodes of the first set of small sensor electrodes, wherein each small sensor electrode of the first set of small sensor electrodes is located on an opposite lateral side of one of the plurality of large sensor electrodes from another small sensor electrode of the first set of small sensor electrodes,
wherein each small sensor electrode of the second set of small sensor electrodes is electrically connected by a second conductive path through a second set of connecting traces to a second pad of the plurality of pads, wherein the first set of conductive paths is non-overlapping with the second set of conductive paths, wherein a second axis crosses two or more of the small sensor electrodes of the second set of small sensor electrodes, wherein each small sensor electrode of the second set of small sensor electrodes is located on an opposite lateral side of one of the plurality of large sensor electrodes from another small sensor electrode of the second set of small sensor electrodes.
16. The method of claim 15, wherein a first conductive path through the first set of connecting traces and the first set of small sensor electrodes passes through the edge region and a routing region bordering the active sensing region opposite the edge region, and wherein a second conductive path through the second set of connecting traces and the second set of small sensor electrodes passes through the edge region and the routing region.
17. The method of claim 15, further comprising providing one or more ground traces in the active sensing region, wherein a number of the plurality of pads in the edge region is less than or equal to one pad for each large sensor electrode of the plurality of sensor electrodes, for each set of electrically connected small sensor electrodes of the plurality of small sensor electrodes, and for each of the one or more ground traces.
18. The method of claim 15, wherein the plurality of pads comprises a pad for each large sensor electrode of the plurality of large sensor electrodes and for each of a plurality of sets of small sensor electrodes, wherein each small sensor electrode in the plurality of sets of small sensor electrodes is electrically coupled to every other small sensor electrode in the same set of small sensor electrodes by a set of connecting traces, wherein the plurality of sets of small sensor electrodes comprises the first set of sensor electrodes and the second set of sensor electrodes.
19. The capacitive sensor array of claim 15, wherein for each small sensor electrode of the plurality of sensor electrodes, a shortest line segment between a geometric center of the small sensor electrode and a central longitudinal axis of a large sensor electrode nearest to the geometric center crosses a ground trace and does not cross any other small electrode, and wherein the first pad is connected at opposite ends of the first pad to two connecting traces of the first set of connecting traces, and wherein the second pad is connected at opposite ends of the second pad to two connecting traces of the second set of connecting traces.
20. The capacitive sensor array of claim 15, wherein a third axis perpendicular to the first axis and the second axis crosses at least one of the first set of small sensor electrodes and at least one of the second set of small sensor electrodes, and wherein a fourth axis parallel to the third axis crosses two or more of the plurality of large sensor electrodes.

1. A circuit breaker having a switching mechanism having an \u2018OFF\u2019 position for manually breaking a circuit, an \u2018ON\u2019 position for manually closing the circuit, and a \u2018TRIP\u2019 position for automatically breaking the circuit, the circuit breaker comprising:
an over current relay configured to generate and output a first trip control signal when an abnormal current on the circuit has been detected, and to generate and output a second trip control signal when a voltage applied to the circuit has been detected as a voltage less than a predetermined reference voltage;
a magnetic trip mechanism electrically connected to the over current relay, and configured to provide a first mechanical driving force when receiving the first trip control signal from the over current relay;
a low voltage trip mechanism electrically connected to the over current relay, and configured to provide a second mechanical driving force when receiving the second trip control signal from the over current relay;
a first micro switch configured to generate and output a first trip indicating signal indicating that the circuit breaker has performed a trip operation due to the occurrence of an abnormal current on the circuit, by converting the first mechanical driving force received from the magnetic trip mechanism into an electric signal;
a second micro switch configured to generate and output a second trip indicating signal indicating that the circuit breaker has performed a trip operation due to the occurrence of a low voltage on the circuit, by converting the second mechanical driving force received from the low voltage trip mechanism into an electric signal;
a first driving force transmission mechanism connected between the first micro switch and the magnetic trip mechanism, and configured to transmit the first mechanical driving force from the magnetic trip mechanism to the first micro switch; and
a second driving force transmission mechanism connected between the second micro switch and the low voltage trip mechanism, and configured to transmit the second mechanical driving force from the low voltage trip mechanism to the second micro switch,

wherein the low voltage trip mechanism comprises an output plunger configured to output the second mechanical driving force, and
wherein the second driving force transmission mechanism comprises a second lever movable to a first position contacting the second micro switch such that the second mechanical driving force output from the output plunger is transmitted to the second micro switch, and a second position separated from the second micro switch when the second mechanical driving force has disappeared.
2. The circuit breaker of claim 1, wherein the magnetic trip mechanism comprises:
a first output lever configured to a first mechanical driving force such that the switching mechanism is triggered to be operated on a trip position; and
a second output lever configured to provide the first mechanical driving force to the first driving force transmission mechanism such that the first mechanical driving force is transmitted to the first micro switch.
3. The circuit breaker of claim 1, wherein the first driving force transmission mechanism comprises:
a first lever rotatable to a first position contacting the first micro switch such that the first mechanical driving force from the magnetic trip mechanism is transmitted to the first micro switch, and a second position separated from the first micro switch; and
a first return spring configured to elastically bias the first lever such that the first lever is moved to the second position from the first position when the first mechanical driving force from the magnetic trip mechanism has disappeared.
4. The circuit breaker of claim 1, wherein the second driving force transmission mechanism further comprises a second return spring configured to elastically bias the second lever such that the second lever is moved to the second position from the first position when the second mechanical driving force has disappeared.
5. The circuit breaker of claim 1, wherein the first micro switch comprises:
a first common terminal;
a first switch connected to the first common terminal;
a first output terminal to which the first switch contacts when the magnetic trip mechanism stops providing the first mechanical driving force as a normal current flows on the circuit of the circuit breaker; and
a second output terminal to which the first switch contacts when the magnetic trip mechanism provides the first mechanical driving force.
6. The circuit breaker of claim 1, wherein the second micro switch comprises:
a second common terminal;
a second switch connected to the second common terminal;
a third output terminal to which the second switch contacts when the low voltage magnetic trip mechanism stops providing the second mechanical driving force; and
a fourth output terminal to which the second switch contacts when the low voltage trip mechanism provides the second mechanical driving force.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An apparatus comprising:
an on screen data (OSD) graphic data receiver which receives OSD graphic data from an external OSD graphic data source; and
a processor which processes the OSD graphic data,
wherein the OSD graphic data receiver further comprises:
a memory which stores the OSD graphic data from the external OSD graphic data source; and
a controller which stores the OSD graphic data in the memory in response to an OSD graphic data storage signal and reads the OSD graphic data from the memory in response to an OSD display signal, to supply the read OSD graphic data to the processor, and
wherein the memory comprises:
a buffer region; and
an OSD region; and
wherein the controller stores the OSD graphic data in the buffer region and stores the OSD graphic data from the buffer region in the OSD region in response to a replacement signal received from a command in putter operated by a user, and supplies the OSD graphic data stored in the OSD region to the processor in response to the OSD display signal.
2. The apparatus of claim 1, wherein the OSD graphic data receiver selects the OSD graphic data from among a plurality of different types of OSD graphic data located at the external OSD graphic data source for display.
3. The apparatus of claim 1, wherein the OSD graphic data receiver comprises:
a broadcast television receiver, which receives a broadcasting signal including the OSD graphic data, to output a composite video signal including the OSD graphic data; and
a data detector which detects the OSD graphic data from the composite video signal;
wherein the processor comprises a video processor which processes the composite video signal and the OSD graphic data detected by the data detector, to output a display video signal including the OSD graphic data.
4. The apparatus of claim 3, wherein the data detector detects the OSD graphic data by detecting data loaded in a line of a vertical blanking interval of the broadcasting signal.
5. The apparatus of claim 4, wherein the OSD graphic data is provided in the broadcasting signal from a broadcasting station in an additional information format of a closed caption mode.
6. The apparatus of claim 1, wherein the OSD graphic data receiver further comprises a cathode ray tube controller which detects a sync signal from the composite video signal and displays the display video signal in accordance with the sync signal.
7. The apparatus of claim 1, wherein:
the buffer region comprises a volatile memory; and
the OSD region comprises a non-volatile memory.
8. An apparatus comprising:
an on screen data (OSD) graphic data receiver which receives OSD graphic data from an external OSD graphic data source;
a processor which processes the OSD graphic data,
wherein the OSD graphic data receiver further comprises:
a memory which stores the OSD graphic data from the external OSD graphic data source; and
a controller which stores the OSD graphic data in the memory in response to an OSD graphic data storage signal and reads the OSD graphic data from the memory in response to an OSD display signal, to supply the read OSD graphic data to the processor; and
an OSD font ROM which permanently stores fixed OSD graphic data, wherein the controller supplies the OSD graphic data from the memory to the processor in a user mode and supplies the fixed OSD graphic data to the processor in a non user mode.
9. The apparatus of claim 1, further comprising an OSD font ROM which permanently stores fixed OSD graphic data, wherein the controller supplies the OSD graphic data from the OSD region to the processor in a user mode and supplies the fixed OSD graphic data to the processor in a non user mode.
10. The apparatus of claim 1, wherein the OSD graphic data is received from a broadcasting station in an RGB pattern and stored in the OSD region in the RGB pattern.
11. The apparatus of claim 1, wherein the OSD graphic data is received from a broadcasting station in a binary code or a hexadecimal code form, converted into an RGB pattern by the controller and stored in the OSD region in the RGB pattern.
12. An apparatus comprising:
an on screen data (OSD) graphic data receiver which receives OSD graphic data from an external OSD graphic data source; and
a processor which processes the OSD graphic data,
wherein the OSD graphic data receiver comprises:
a tuner which receives a television signal, to output a composite video signal;
a modem connected to a communication network, which downloads the OSD graphic data from an external OSD graphic data source;
a video processor which processes the composite video signal and the OSD graphic data downloaded by the modem, to output a display video signal including the OSD graphic data,
a memory which stores the OSD graphic data downloaded by the modem; and
a controller which stores the OSD graphic data downloaded by the modem in the memory in response to an OSD graphic data storage signal and reads the OSD graphic data from the memory in response to an OSD display signal, to supply the OSD graphic data to the video processor,
wherein the memory comprises:
a buffer region; and
an OSD region; and
wherein the controller stores the OSD graphic data in the buffer region and stores the OSD graphic data from the buffer region in the OSD region in response to a replacement signal received from a command inputter operated by a user, and supplies the OSD graphic data stored in the OSD region to the video processor in response to the OSD display signal.
13. The apparatus of claim 12, wherein the OSD graphic data receiver further comprises a cathode ray tube controller which detects a sync signal from the composite video signal and displays the display video signal in accordance with the sync signal.
14. The apparatus of claim 12, wherein the external OSD graphic data source is an OSD graphic data providing server.
15. The apparatus of claim 12, wherein the external OSD graphic data source is an OSD graphic data providing server, and the controller downloads the OSD graphic data via the modem from a home page of the OSD graphic data providing server.
16. The apparatus of claim 12, wherein:
the buffer region comprises a volatile memory; and
the OSD region comprises a non-volatile memory.
17. An apparatus comprising:
an on screen data (OSD) graphic data receiver which receives OSD graphic data from an external OSD graphic data source;
a processor which processes the OSD graphic data,
wherein the OSD graphic data receiver comprises:
a tuner which receives a television signal, to output a composite video signal;
a modem connected to a communication network, which downloads the OSD graphic data from an external OSD graphic data source;
a video processor which processes the composite video signal and the OSD graphic data downloaded by the modem, to output a display video signal including the OSD graphic data,
a memory which stores the OSD graphic data downloaded by the modem; and
a controller which stores the OSD graphic data downloaded by the modem in the memory in response to an OSD graphic data storage signal and reads the OSD graphic data from the memory in response to an OSD display signal, to supply the OSD graphic data to the video processor; and
an OSD font ROM which permanently stores fixed OSD graphic data, wherein the controller supplies the OSD graphic data from the memory to the video processor in a user mode and supplies the fixed OSD graphic data to the video processor in a non user mode.
18. The apparatus of claim 12, further comprising an OSD font ROM which permanently stores fixed OSD graphic data, wherein the controller supplies the OSD graphic data from the OSD region to the video processor in a user mode and supplies the fixed OSD graphic data to the video processor in a non user mode.
19. An apparatus comprising:
an on screen data (OSD) graphic data receiver which receives OSD graphic data from an external OSD graphic data source; and
a processor which processes the OSD graphic data,
wherein the OSD graphic data receiver comprises:
a camera which picks up an image of an object, to output a composite video signal;
a modem connected to a communication network, which downloads the OSD graphic data from an external OSD graphic data source;
a video processor which processes the composite video signal and the OSD graphic data downloaded by the modem, to output a display video signal including the OSD graphic data,
a memory which stores the OSD graphic data downloaded by the modem; and
a controller which stores the OSD graphic data downloaded by the modem in the memory in response to an OSD graphic data storage signal and reads the OSD graphic data from the memory in response to an OSD display signal, to supply the OSD graphic data to the video processor,
wherein the memory comprises:
a buffer region; and
an OSD region; and
wherein the controller stores the OSD graphic data in the buffer region and stores the OSD graphic data from the buffer region in the OSD region in response to a replacement signal received from a command inputter operated by a user, and supplies the OSD graphic data stored in the OSD region to the video processor in response to the OSD display signal.
20. The apparatus of claim 19, wherein the external OSD graphic data source is an OSD graphic data providing server.
21. The apparatus of claim 19, wherein the external OSD graphic data source is an OSD graphic data providing server, and the controller downloads the OSD graphic data via the modem from a home page of the OSD graphic data providing server.
22. The apparatus of claim 19, wherein:
the buffer region comprises a volatile memory; and
the OSD region comprises a non-volatile memory.
23. An apparatus comprising:
an on screen data (OSD) graphic data receiver which receives OSD graphic data from an external OSD graphic data source;
a processor which processes the OSD graphic data,wherein the OSD graphic data receiver comprises:
a camera which picks up an image of an object, to output a composite video signal,
a modem connected to a communication network, which downloads the OSD graphic data from an external OSD graphic data source,
a video processor which processes the composite video signal and the OSD graphic data downloaded by the modem, to output a display video signal including the OSD graphic data,
a memory which stores the OSD graphic data downloaded by the modem, and
a controller which stores the OSD graphic data downloaded by the modem in the memory in response to an OSD graphic data storage signal and reads the OSD graphic data from the memory in response to an OSD display signal, to supply the OSD graphic data to the video processor; and
an OSD font ROM which permanently stores fixed OSD graphic data, wherein the controller supplies the OSD graphic data from the memory to the video processor in a user mode and supplies the fixed OSD graphic data to the video processor in a non user mode.
24. The apparatus of claim 19, further comprising an OSD font ROM which permanently stores fixed OSD graphic data, wherein the controller supplies the OSD graphic data from the OSD region to the video processor in a user mode and supplies the fixed OSD graphic data to the video processor in a non user mode.
25. The apparatus of claim 19, further comprising a deck which records the display video signal on a recording medium.
26. The apparatus of claim 19, wherein:
the OSD graphic data is supplied to the video processor as an OSD-RGB signal;
the video processor processes luminance and chrominance signals of the composite video signal, overlaps the processed luminance and chrominance signals with the OSD-RGB signal, and FM-modulates the overlapped signal; and further comprising:
a deck which records the FM-modulated overlapped signal on a recording medium.
27. A television receiver set comprising:
a receiver receiving a television signal, to output a composite video signal;
a video processor processing the composite video signal and overlapping the processed composite video signal and an on screen display (OSD) graphic signal, to output a display video signal;
a data detector detecting OSD graphic data from the composite video signal;
a memory storing the detected OSD graphic data; and
a controller storing the OSD graphic data detected from the data detector in the memory in response to an OSD graphic data storage signal and reading the OSD graphic data from the memory in response to an OSD display signal, to supply the read OSD graphic data to the video processor as the OSD graphic signal,
wherein the memory comprises:
a buffer region; and
an OSD region; and
wherein the controller stores the OSD graphic data in the buffer region and stores the OSD graphic data from the buffer region in the OSD region in response to a replacement signal received from a command in putter operated by a user, and supplies the OSD graphic data stored in the OSD region to the video processor in response to the OSD display signal.
28. A web television receiver set comprising:
a receiver receiving a television signal, to output a composite video signal;
a video processor processing the composite video signal and overlapping the processed composite video signal and an on screen display (OSD) graphic signal, to output a display video signal;
a modem connected to a communication network, downloading OSD graphic data from an external OSD graphic data source;
a memory storing the OSD graphic data downloaded via the modem; and
a controller storing the OSD graphic data downloaded via the modem in the memory in response to an OSD graphic data downloading signal and reading the OSD graphic data from the memory in response to an OSD display signal, to supply the read OSD graphic data to the video processor as the OSD graphic signal,
wherein the memory comprises:
a buffer region; and
an OSD region; and
wherein the controller stores the OSD graphic data in the buffer region and stores the OSD graphic data from the buffer region in the OSD region in response to a replacement signal received from a command inputter operated by a user, and supplies the OSD graphic data stored in the OSD region to the video processor in response to the OSD display signal.
29. A web video camera apparatus comprising:
a camera picking up an image, to output a video signal;
a video processor processing the video signal and overlapping the processed video signal and an on screen display (OSD) graphic signal, to output a display video signal;
a modem connected to a communication network, downloading OSD graphic data from an external OSD graphic data source;
a memory storing the OSD graphic data downloaded via the modem;
a deck recording the display video signal on a video recording medium; and
a controller storing the OSD graphic data downloaded via the modem in the memory in response to an OSD graphic data downloading signal and reading the OSD graphic data from the memory in response to an OSD display signal, to supply the read OSD graphic data to the video processor as the OSD graphic signal,
wherein the memory comprises:
a buffer region; and
an OSD region; and
wherein the controller stores the OSD graphic data in the buffer region and stores the OSD graphic data from the buffer region in the OSD region in response to a replacement signal received from a command inputter operated by a user, and supplies the OSD graphic data stored in the OSD region to the video processor in response to the OSD display signal.
30. An MP3 player comprising:
a receiver receiving an on screen display (OSD) graphic signal from an external source;
a processor processing the OSD graphic signal, to output a display video signal;
a memory storing the OSD graphic data; and
a controller storing the OSD graphic data in the memory in response to an OSD graphic data storage signal and reading the OSD graphic data from the memory in response to an OSD display signal, to supply the read OSD graphic data to the processor as the OSD graphic signal,
wherein the memory comprises:
a buffer region; and
an OSD region; and
wherein the controller stores the OSD graphic data in the buffer region and stores the OSD graphic data from the buffer region in the OSD region in response to a replacement signal received from a command inputter operated by a user, and supplies the OSD graphic data stored in the OSD region to the processor in response to the OSD display signal.
31. The MP3 player of claim 30, wherein the external source is a personal computer.
32. A method of displaying on screen display (OSD) graphic data comprising:
receiving the OSD graphic data in a device from an external OSD graphic data source; and
displaying the OSD graphic data in a first mode,
wherein the receiving comprises:
storing the OSD graphic data received from the external OSD graphic data source in a buffer region in response to an OSD graphic data receiving input signal from the user; and
storing the OSD graphic data from the buffer region in an OSD region in response to a replacement signal from the user.
33. The method of claim 32, wherein the external OSD graphic data source is a broadcasting station and the receiving further comprises receiving the OSD graphic data in a television signal from the broadcasting station.
34. The method of claim 33, wherein the displaying comprises:
overlapping the OSD graphic data with a television signal received from the broadcasting station; and
displaying the overlapped signal.
35. The method of claim 32, wherein the external OSD graphic data source is an OSD graphic data providing server and the receiving further comprises receiving the OSD graphic data from the OSD graphic data providing server through a communication network.
36. The method of claim 35, wherein the displaying comprises:
overlapping the OSD graphic data with a television signal received from broadcasting station; and
displaying the overlapped signal.
37. The method of claim 35, wherein the displaying comprises:
overlapping the OSD graphic data with an image signal indicative of an image object received through a lens;,and
displaying the overlapped signal.
38. The method of claim 32, wherein the device comprises a font ROM having fixed OSD graphic data, the method comprising:
determining whether the device is in an OSD display mode;
determining whether the device is in a user mode or a non user mode if the device is in the OSD display mode; and
reading and displaying the OSD graphic data from the buffer region if the device is in the user mode and the fixed OSD graphic data from the font ROM if the device is in the non user mode.