Author: claimsbot

1. A radiation detection device comprising:
an optical detector pixel array having one or more pixel cells which can be triggered by optical photons;
a timestamp trigger unit in operative communication with at least one timing unit;

wherein the timestamp trigger unit is configured to receive signals from the optical detector pixel array and is further configured to determine at least a first pixel cell triggering rate for the one or more pixel cells within the optical detector pixel array;
wherein the at least a first pixel cell triggering rate is determined by computing the number of triggered pixel cells within the optical detector pixel array within a predetermined delay period;
wherein the timestamp trigger unit is configured to cause the at least one timing unit to generate a first timestamp indicative of the end of the predetermined delay period based on the at least a first pixel cell triggering rate for the one or more pixel cells (9) within the optical detector pixel array.
2. A radiation detection device according to claim 1 wherein the timestamp trigger unit is configured to cause the at least one timing unit to generate the first timestamp if the at least a first pixel cell triggering rate for the one or more pixel cells within the optical detector pixel array exceeds a threshold rate value.
3. (canceled)
4. A radiation detection device according to claim 1 wherein the first timestamp is generated based further upon a triggered pixel cell count for the one or more pixel cells within the optical detector pixel array;
wherein the first timestamp is generated if the triggered pixel cell count meets a predetermined triggered pixel cell count condition prior to the at least a first pixel cell triggering rate meeting a predetermined pixel cell triggering rate condition.
5. A radiation detection device according to claim 4 wherein the predetermined triggered pixel cell count condition is that the triggered pixel cell count exceeds a threshold count value;
and wherein the predetermined pixel cell triggering rate condition is that the at least a first pixel cell triggering rate exceeds a threshold rate value;
and wherein the predetermined delay period begins when the triggered pixel cell count exceeds the threshold count value;
such that the at least one timing unit is caused to generate the first timestamp if the triggered pixel cell count exceeds the threshold count value and then subsequently exceeds a higher count value before the end of the predetermined delay period such that the threshold rate value is exceeded.
6. A radiation detection device according to claim 4 further comprising a timestamp adjustment unit configured to receive the first timestamp from the at least one timing unit;
wherein the timestamp adjustment unit is configured to generate an adjusted first timestamp indicative of the time at which the predetermined triggered pixel cell count condition was met by subtracting the predetermined delay period from the time of the first timestamp.
7. A radiation detection device according to claim 1 wherein the timestamp trigger unit is configured to cause the at least one timing unit to generate the first timestamp based further on a second pixel cell triggering rate for the one or more pixel cells within the optical detector pixel array and wherein the second pixel cell triggering rate is determined at a later point in time to the first pixel cell triggering rate.
8. A radiation detection device according to claim 7 wherein the timestamp trigger unit is configured to cause the at least one timing unit to generate the first timestamp if the first pixel cell triggering rate for the one or more pixel cells within the optical detector pixel array exceeds a first threshold rate and the second pixel cell triggering rate for the one or more pixel cells within the optical detector pixel array exceeds a second threshold rate.
9. A radiation detection device according to claim 1 further comprising at least a second timing unit;
wherein the at least a second timing unit is in communication with the timestamp trigger unit;
wherein the timestamp trigger unit is further configured to cause the at least a second timing unit to generate a photon count timestamp indicative of the time of detection of one or more optical photons by pixel cells within the optical detector pixel array.
10. A radiation detection device according to claim 1 further comprising at least a second timing unit;
wherein the at least a second timing unit is in communication with the timestamp trigger unit;
wherein the timestamp trigger unit is further configured to cause the at least a second timing unit to generate a triggering rate timestamp indicative of the time at which the pixel cell triggering rate for the one or more pixel cells within the optical detector pixel array meets a second triggering rate condition.
11. A PET imaging system comprising a plurality of radiation detection devices according to claim 1;
wherein each radiation detection device further comprises a scintillator element in optical communication with the optical detector pixel array.
12. A PET imaging system comprising a plurality of radiation detection devices according to claim 9;
wherein each radiation detection device further comprises a scintillator element in optical communication with the optical detector pixel array;
the PET imaging system further comprising:
a depth-of-interaction calculation unit;
wherein the depth-of-interaction calculation unit is configured to compute a depth of interaction of a radiation quant in the scintillator element based on either i) the time difference between the first timestamp and the photon count timestamp or ii) the time difference between the first timestamp and the triggering rate timestamp.
13. A PET imaging system comprising a plurality of radiation detection devices according to claim 9;
wherein each radiation detection device further comprises a scintillator element in optical communication with the optical detector pixel array;
the PET imaging system further comprising a timestamp correction unit configured to generate a corrected timestamp based on a weighted average of the first timestamp and the second timestamp.
14. A timing method for use in PET imaging or Cherenkov imaging, the timing method comprising the steps of:
receiving signals from an optical detector pixel array indicative of the triggering of one or more pixel cells within the optical detector pixel array;
determining at least a first pixel cell triggering rate for the one or more pixel cells within the optical detector pixel array by computing the number of triggered pixel cells within the optical detector pixel array within a predetermined delay period;
generating a first timestamp that is indicative of the end of the predetermined delay period and is also indicative of the detection of a radiation quant based on the at least a first pixel cell triggering rate for the one or more pixel cells within the optical detector pixel array.
15. A computer program product comprising computer executable instructions to perform the method steps of:
receiving signals from an optical detector pixel array indicative of the triggering of one or more pixel cells within the optical detector pixel array;
determining at least a first pixel cell triggering rate for the one or more pixel cells within the optical detector pixel array by computing the number of triggered pixel cells within the optical detector pixel array predetermined delay period;
generating a first timestamp that is indicative of the end of the predetermined delay period and is also indicative of the detection of a radiation quant based on the at least a first pixel cell triggering rate for the one or more pixel cells within the optical detector pixel array.
16. A computer program product according to claim 15 wherein the computer executable instructions are further configured to perform the method step of:
generating an adjusted first timestamp by subtracting the predetermined delay period from the time of the first timestamp.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A semiconductor device comprising:
an input terminal,
an output terminal,
a first terminal,
a second terminal,
a third terminal, and
a fourth terminal;
a first transistor for transmitting electric potential of the first terminal to the output terminal;
a second transistor which fixes electric potential of the output terminal by conducting electricity between the output terminal and the second terminal in accordance with electric potential of the fourth terminal; and
a third transistor which fixes electric potential of the third terminal by conducting electricity between the third terminal and the second terminal in accordance with the electric potential of the fourth terminal,
wherein a first pulse is configured to be input from the input terminal, and
wherein a second pulse reversed to the first pulse is configured to be input from the fourth terminal.
2. The semiconductor device according to claim 1, wherein an average of an area of an gate electrode of the second transistor and an area of an gate electrode of the third transistor is larger than an area of an gate electrode of the first_transistor.
3. The semiconductor device according to claim 1, wherein a wiring electrically connected to the second terminal and a wiring electrically connected to the first terminal are provided on a side opposite to the output terminal with respect to the first transistor, the second transistor, and the third transistor.
4. The semiconductor device according to claim 1, further comprising a first wiring layer, a second wiring layer, a third wiring layer, an insulating film, and an interlayer insulating film, and wherein the insulating film is provided between the first wiring layer and the second wiring layer,
wherein the interlayer insulating film is formed between the second wiring layer and the third wiring layer,
wherein the interlayer insulating film is thicker than the insulating film,
wherein a first electrode electrically connected to the first terminal comprises a part of_the second wiring layer,
wherein a second electrode electrically connected to the output terminal comprises at least a part of the first wiring layer and a part of the third wiring layer, and
wherein at a region where the second electrode electrically connected to the output terminal and the first electrode electrically connected to the first terminal are crossed, the second electrode electrically connected to the output terminal comprises a part of the third wiring layer.
5. A display device comprising a semiconductor device according to claim 1, further comprising an external driver circuit, and a connection wiring substrate, wherein the semiconductor device and the external driver circuit are connected to each other with one connection wiring substrate.
6. An electronic device using the display device according to claim 5.
7. A semiconductor device comprising:
an input terminal,
an output terminal,
a first terminal,
a second terminal,
a third terminal,
a fourth terminal, and
a fifth terminal;
a first transistor for transmitting electric potential of the first terminal to the output terminal;
a rectifying element which turns ON the first transistor in accordance with electric potential of the input terminal;
a second transistor which fixes electric potential of the output terminal by conducting electricity between the output terminal and the second terminal in accordance with electric potential of the fifth terminal;
a third transistor which fixes electric potential of the third terminal by conducting electricity between the third terminal and the second terminal in accordance with electric potential of the fourth terminal; and
a circuit which reverses the electric potential of the third terminal and outputs the electric potential to the fifth terminal,
wherein a first pulse is configured to be input from the input terminal, and
wherein a second pulse reversed to the first pulse is configured to be input from the fourth terminal.
8. The semiconductor device according to claim 7, wherein an average of an area of an gate electrode of the second transistor and an area of an gate electrode of the third transistor is larger than an area of an gate electrode of the first_transistor.
9. The semiconductor device according to claim 7, wherein a wiring electrically connected to the second terminal and a wiring electrically connected to the first terminal are provided on a side opposite to the output terminal with respect to the first transistor, the second transistor, and the third transistor.
10. The semiconductor device according to claim 7, further comprising a first wiring layer, a second wiring layer, a third wiring layer, an insulating film, and an interlayer insulating film, and wherein the insulating film is provided between the first wiring layer and the second wiring layer,
wherein the interlayer insulating film is formed between the second wiring layer and the third wiring layer,
wherein the interlayer insulating film is thicker than the insulating film,
wherein a first electrode electrically connected to the first terminal comprises a part of_the second wiring layer,
wherein a second electrode electrically connected to the output terminal comprises at least a part of the first wiring layer and a part of the third wiring layer, and
wherein at a region where the second electrode electrically connected to the output terminal and the first electrode electrically connected to the first terminal are crossed, the second electrode electrically connected to the output terminal comprises a part of the third wiring layer.
11. A display device comprising a semiconductor device according to claim 7, further comprising an external driver circuit, and a connection wiring substrate, wherein the semiconductor device and the external driver circuit are connected to each other with one connection wiring substrate.
12. An electronic device using the display device according to claim 11.
13. A semiconductor device comprising:
an input terminal,
an output terminal,
a first terminal,
a second terminal,
a third terminal,
a fourth terminal,
a fifth terminal, and
a sixth terminal;
a first transistor for transmitting electric potential of the first terminal to the output terminal;
a first rectifying element which turns ON the first transistor in accordance with electric potential of the input terminal;
a second transistor which fixes electric potential of the output terminal by conducting electricity between the output terminal and the second terminal in accordance with electric potential of the fourth terminal;
a third transistor which fixes electric potential of the third terminal by conducting electricity between the third terminal and the second terminal in accordance with the electric potential of the fourth terminal;
a second rectifying element for increasing electric potential of the fifth terminal in accordance with the electric potential of the output terminal; and
a fourth transistor for lowering electric potential of the sixth terminal by conducting electricity between the second terminal and the sixth terminal,
wherein the fourth terminal is electrically connected to one of source and drain of a fifth transistor.
14. The semiconductor device according to claim 13, wherein an average of an area of an gate electrode of the second transistor and an area of an gate electrode of the third transistor is larger than an area of an gate electrode of the first_transistor.
15. The semiconductor device according to claim 13, wherein a wiring electrically connected to the second terminal and a wiring electrically connected to the first terminal are provided on a side opposite to the output terminal with respect to the first transistor, the second transistor, and the third transistor.
16. The semiconductor device according to claim 13, further comprising a first wiring layer, a second wiring layer, a third wiring layer, an insulating film, and an interlayer insulating film, and wherein the insulating film is provided between the first wiring layer and the second wiring layer,
wherein the interlayer insulating film is formed between the second wiring layer and the third wiring layer,
wherein the interlayer insulating film is thicker than the insulating film,
wherein a first electrode electrically connected to the first terminal comprises a part of the second wiring layer,
wherein a second electrode electrically connected to the output terminal comprises at least a part of the first wiring layer and a part of the third wiring layer, and
wherein at a region where the second electrode electrically connected to the output terminal and the first electrode electrically connected to the first terminal are crossed, the second electrode electrically connected to the output terminal comprises a part of the third wiring layer.
17. The display device comprising a semiconductor device according to claim 13, further comprising an external driver circuit, and a connection wiring substrate, wherein the semiconductor device and the external driver circuit are connected to each other with one connection wiring substrate.
18. The electronic device using the display device according to claim 17.
19. The semiconductor device according to claim 13, wherein the first, second, third and fourth transistors have a same polarity.
20. The semiconductor device according to claim 19, further comprising:
a circuit comprising all transistors comprising the first, second, third and fourth transistors,
wherein all the transistors have the same polarity.

1. A processor comprising:
a thermoelectric cooling (TEC) controller to:
obtain a platform cooling level associated with the processor;
obtain a temperature associated with the processor;
calculate a TEC power level based at least in part on the platform cooling level and the temperature; and
provide the TEC power level to a TEC device associated with the processor, wherein the TEC device is to transfer heat from the processor to a heat sink.
2. The processor of claim 1, wherein the platform cooling level is a first level for a fan providing an air flow to the heat sink.
3. The processor of claim 2, wherein the TEC controller is further to calculate a second level for the fan.
4. The processor of claim 3, wherein the TEC controller is further to calculate a virtual temperature based on the second level for the fan.
5. The processor of claim 4, wherein the TEC controller is further to store the virtual temperature in a register accessed by a platform cooling logic.
6. The processor of claim 2, wherein the TEC device is to provide a first heat flow from the processor to the heat sink.
7. The processor of claim 6, wherein the TEC controller is to calculate the TEC power level by balancing the first heat flow with a convective heat flow associated with the air flow.
8. The processor of claim 7, wherein the TEC controller is to balance the first heat flow and the convective heat flow using a balancing algorithm.
9. The processor of claim 1, wherein the TEC controller is further to generate a duty cycle signal based on the TEC power level.
10. The processor of claim 9, wherein the TEC controller is further to switch a power input to the TEC device using the duty cycle signal.
11. The processor of claim 9, wherein the duty cycle signal is a pulse width modulated (PWM) signal.
12. A processor comprising:
a plurality of cores to execute a plurality of instructions;
a first thermoelectric cooling (TEC) device to provide localized cooling to a first core of the plurality of cores;
logic to determine a predicted heat load on the first core associated with executing a first portion of the plurality of instructions; and
a TEC controller to control, based on the predicted heat load, a power level of the first TEC device when the first core is executing the first portion of the plurality of instructions.
13. The processor of claim 12, wherein at least one of the plurality of cores comprises:
at least one core component; and
a second TEC device to provide localized cooling to the at least one core component.
14. The processor of claim 12, further comprising:
at least one uncore component; and
a third TEC device to provide localized cooling to the at least one uncore component.
15. The processor of claim 12, wherein each core of the plurality of cores includes instruction monitoring logic to monitor one or more instructions to be executed by the core.
16. The processor of claim 12, wherein the processor is coupled to a dynamic random access memory (DRAM).
17. A method, comprising:
determining a current level of a platform cooling device;
determining a temperature of an electronic device;
calculating, based at least on the current level and the temperature, a power level for a thermoelectric cooling (TEC) device, wherein the TEC device is to transfer heat from the electronic device to the platform cooling device.
18. The method of claim 17, further comprising calculating a second level of the platform cooling device.
19. The method of claim 18, further comprising programming the second level using a dedicated interface to the platform cooling device.
20. The method of claim 18, wherein calculating the power level for the TEC device comprises balancing a cooling effect of the TEC device with a cooling effect of the platform cooling device.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method comprising:
receiving data for storage on a non-volatile recording medium, the non-volatile recording medium comprising an array of cells, each cell encoding a number of states per cell;
converting the data from a binary representation to a non-binary representation corresponding to the number of states per cell; and
storing the converted data to the array of cells.
2. The method of claim 1, wherein each cell of the array of cells encodes an ordered sequence of states, and storing the converted data to the array of cells comprises iteratively selecting cells that encode a data value other than a desired value from the converted data, and programming the selected cells to a next state in the ordered sequence of states, until the converted data is stored.
3. The method of claim 2, wherein selecting cells comprises marking bits associated with the selected cells in a write buffer for the array of cells.
4. The method of claim 2, wherein programming a cell to an intermediate state in the ordered sequence of states comprises changing a programming level for the cell to a program value other than a target program value for the intermediate state.
5. The method of claim 1, wherein storing the converted data to the array of cells comprises changing a programming level for at least one cell without verifying the change to the programming level.
6. The method of claim 1, wherein each cell of the array of cells encodes an ordered sequence of states, and storing the converted data to the array of cells comprises iteratively selecting cells for programming to a highest unprogrammed state in the ordered sequence of states, and programming the selected cells, until the converted data is stored.
7. The method of claim 1, further comprising:
reading the converted data from the array of cells;
translating the converted data to binary data; and
returning the binary data to one or more of a host device and a storage controller for the non-volatile recording medium.
8. The method of claim 7, wherein reading the converted data from the array of cells comprises setting a plurality of read thresholds for the array of cells and sensing cells that satisfy the read thresholds, until a state is determined for each cell in the array of cells.
9. The method of claim 8, wherein reading the converted data further comprises:
setting at least one additional read threshold in response to determining a state for each cell;
sensing cells that satisfy the at least one additional read threshold; and
detecting errors in the converted data using information derived from sensing cells that satisfy the at least one additional read threshold.
10. The method of claim 1, further comprising dynamically adjusting the number of states per cell over time.
11. The method of claim 10, wherein the number of states per cell is adjusted based on a health characteristic of the array of cells.
12. The method of claim 1, further comprising using an error correcting algorithm that operates on non-binary numbers to detect errors in the converted data.
13. An apparatus comprising:
an interface module configured to receive data for storage on a non-volatile memory medium, the non-volatile memory medium comprising an array of cells, each cell encoding a number of abodes per cell with a non-binary alignment;
a base conversion module configured to convert the data from a binary representation to a representation in a non-binary base, the non-binary base using a number of unique digits equal to the non-binary aligned number of abodes per cell; and
a write module configured to store the converted data to the array of cells.
14. The apparatus of claim 13, wherein each cell of the array of cells encodes an ordered sequence of abodes, and the write module is configured to store the converted data to the array of cells by iteratively selecting cells that encode a data value other than a desired value from the converted data, and programming the selected cells to a next abode in the ordered sequence of abodes, until the converted data is stored.
15. The apparatus of claim 13, wherein each cell of the array of cells encodes an ordered sequence of abodes, and the write module is configured to store the converted data to the array of cells by iteratively selecting cells for programming to a highest unprogrammed abode in the ordered sequence of abodes, and programming the selected cells, until the converted data is stored.
16. The apparatus of claim 13, wherein the base conversion module is further configured to separate a binary stream for the data into a plurality of binary numbers and to convert each binary number to the non-binary base, each binary number comprising a number of bits less than or equal to a word unit size for the array of cells.
17. The apparatus of claim 13, further comprising:
a read module configured to read the converted data from the array of cells;
a translate module configured to translate the converted data to binary data; and
a return module configured to return the binary data to one or more of a host device and a storage controller for the non-volatile memory medium.
18. The apparatus of claim 13, further comprising an abode adjust module configured to dynamically adjust the number of abodes per cell over time based on a health characteristic of the array of cells.
19. The apparatus of claim 13, further comprising an error module configured to use an error correcting algorithm that operates on non-binary numbers to detect errors in the converted data.
20. An apparatus comprising:
means for receiving data for storage on a non-volatile storage medium, the non-volatile storage medium comprising an array of cells, each cell encoding a non-power-of-two number of encoding states per cell;
means for converting the data from a binary representation to a representation in a non-binary base, the non-binary base using a number of unique digits equal to the number of encoding states per cell for storage by the non-volatile storage medium; and
means for dynamically adjusting the number of states per cell over time.
21. The apparatus of claim 20, further comprising:
means for storing the converted data to the array of cells;
means for reading the converted data from the array of cells;
means for translating the converted data to binary data; and
means for returning the binary data to one or more of a host device and a storage controller for the non-volatile storage medium.
22. A system comprising:
a non-volatile recording device comprising a non-volatile recording medium, the non-volatile recording medium comprising an array of cells, each cell encoding a non-power-of-two number of states per cell, the non-volatile recording device in communication with a host device over a communications bus; and
a write pipeline comprising,
an interface module configured to receive data for storage on the non-volatile recording medium;
a base conversion module configured to convert the data from a binary representation to a representation in a non-base-two base, the non-base-two base using a number of unique digits equal to the non-power-of-two number of states per cell; and
a write module configured to store the converted data to the array of cells.
23. The system of claim 22, further comprising a read pipeline, the read pipeline comprising:
a read module configured to read the converted data from the array of cells;
a translate module configured to translate the converted data to binary data; and
a return module configured to return the binary data to one or more of a host device and a storage controller for the non-volatile recording medium.
24. A computer program product comprising a computer readable storage medium storing computer usable program code executable to perform operations, the operations comprising:
reading non-binary data from a non-volatile memory medium, the non-volatile memory medium comprising an array of cells, each cell encoding a number of abodes per cell other than a power of two, the non-binary data encoded in a non-binary base, the non-binary base using a number of unique digits equal to the number of abodes per cell;
translating the non-binary data to binary data; and
returning the binary data to one or more of a host device and a storage controller for the non-volatile memory medium.
25. The computer program product of claim 24, wherein reading the non-binary data from the non-volatile memory medium comprises:
setting a plurality of read thresholds for the array of cells;
sensing cells that satisfy the read thresholds, until an abode is determined for each cell in the array of cells;
setting at least one additional read threshold in response to determining am abode for each cell;
sensing cells that satisfy the at least one additional read threshold; and
detecting errors in the non-binary data using information derived from sensing cells that satisfy the at least one additional read threshold.