Author: claimsbot

1. A power supply system for a telecommunications facility, comprising:
a liquid source;
a vaporizing system for the vaporization of a liquid from said liquid source into a vaporous fuel, said vaporizing system including a ventilated housing which is associated with a heater which is adapted to blow heated air across a portion of said vaporization system for the purpose of avoiding the development of frozen condensate on said vaporizing system, said vaporization resulting in heat absorption;
a cooling system which is adapted to use said heat absorption for cooling said facility; and
a generator which generates electric current using said vaporous fuel.
2. The system of claim 1, wherein said liquid comprises hydrogen.
3. The system of claim 1, wherein said generator comprises an internal combustion engine.
4. The system of claim 3, wherein said internal combustion engine is piston driven.
5. The system of claim 1, wherein said generator includes a proton exchange membrane.
6. The system of claim 1, wherein said electric current comprises alternating current.
7. The system of claim 1, wherein said electric current comprises direct current.
8. The system of claim 1, wherein said cooling system comprises:
a first heat transfer device which absorbs heat into at least one of a liquid and vaporous hydrogen from a heat transfer medium, said heat transfer medium being useable for cooling purposes.
9. The system of claim 8 wherein said heat transfer medium is a fluid.
10. The system of claim 9 wherein said fluid comprises ethylene glycol.
11. The system of claim 10 wherein said fluid comprises water.
12. The system of claim 8 wherein said heat transfer medium is a refrigerant.
13. The system of claim 8 further comprising a second heat transfer device which accepts said heat transfer medium from said first heat transfer device and uses said heat transfer medium for cooling purposes.
14. The system of claim 8, wherein said first heat transfer device is incorporated into said vaporizing system.
15. The system of claim 1, wherein said cooling system is used for air conditioning in the facility.
16. The system of claim 1, wherein said heater receives heat energy from a heat-delivering medium, said heat energy being drawn from a power-generating device.
17. The system of claim 16, wherein said power-generating device produces electricity.
18. The system of claim 16, wherein said power-generating device is said generator.
19. The system of claim 18, wherein said generator comprises an internal combustion engine.
20. The system of claim 19, wherein said heat-delivering medium is also used to cool the internal combustion engine.
21. The system of claim 20, wherein said heat-delivering medium is run through an engine jacket of the internal combustion engine and transmitted using an engine-jacket pump.
22. A method of supplying power for use in a telecommunications facility, comprising:
providing a liquid source;
vaporizing the liquid into a vaporous fuel using a conduit, blowing heated air past said conduit to prevent the development of frozen condensate thereon, said vaporization resulting in heat absorption;
using said heat absorption for cooling purposes in the telecommunications facility; and
generating electric current using said vaporous fuel.
23. The method of claim 22, comprising:
selecting hydrogen as the liquid.
24. The method of claim 22, comprising:
combusting the vaporous fuel in accomplishing the generating step.
25. The method of claim 22, comprising:
combusting the vaporous fuel in a piston-driven internal combustion engine in accomplishing the generating step.
26. The method of claim 22, comprising:
introducing the vaporous fuel into a proton exchange membrane in accomplishing said generating step.
27. The method of claim 22, comprising:
absorbing heat into at least one of said liquid and vaporous hydrogen from a heat transfer medium; and
using said heat transfer medium for cooling purposes.
28. The method of claim 27, comprising:
selecting a fluid to serve as the heat transfer medium.
29. The method of claim 27, comprising:
selecting ethylene glycol to comprise a part of said heat transfer medium.
30. The method of claim 27, comprising:
receiving said heat transfer medium after said heat has been absorbed out of it; and
cooling with said heat transfer medium.
31. The method of claim 30, comprising:
air conditioning a portion of said facility using cooling provided by said heat transfer medium.
32. The method of claim 22, comprising:
including said conduit in a housing;
ventilating said housing; and
transmitting said heated air in and out of said housing.
33. The method of claim 22, comprising:
drawing heat energy from a power-generating device in creating said heated air.
34. The method of claim 22, comprising:
drawing heat energy from an internal combustion engine in creating said heated air.
35. The method of claim 22, comprising:
drawing heat energy from the same device used to accomplish said generating step in creating said heated air.
36. The method of claim 22, comprising:
deriving a heat-delivering medium from a power-generating device in creating said heated air.
37. The method of claim 36, comprising:
selecting as said heat-delivering medium a fluid used to cool said power-generating device.
38. The method of claim 37, comprising:
pumping said heat-delivering medium from an engine jacket on said power-generating device in creating said heated air; and
returning said heat-delivering medium to said engine jacket after it has been used in creating said heated air.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A phase change memory device comprising:
a semiconductor substrate;
a plurality of cell arrays stacked above said semiconductor substrate, each cell array having memory cells arranged in a matrix manner for storing resistance values as data that are determined by phase change of said memory cells, bit lines each commonly connecting one ends of plural memory cells arranged in a first direction of said matrix and word lines each commonly connecting the other ends of plural memory cells arranged in a second direction of said matrix;
a readwrite circuit formed on said semiconductor substrate as underlying said cell arrays for reading and writing data of said cell arrays;
first and second vertical wirings disposed outside of first and second boundaries that define a cell layout region of said cell arrays in said first direction to connect said bit lines of the respective cell arrays to said readwrite circuit; and
third vertical wirings disposed outside of one of third and fourth boundaries that define said cell layout region in said second direction to connect said word lines of the respective cell arrays to said readwrite circuit.
2. The phase change memory device according to claim 1, wherein
each said memory cell has a stack structure of a chalcogenide and a diode as disposed at each cross portion of said bit lines and word lines in the respective cell arrays.
3. The phase change memory device according to claim 2, wherein
said diode of said memory cell is serially connected to said chalcogenide while having a polarity with said bit line side as a cathode and with said word line side as an anode, and wherein
said bit lines and word lines are so potentially fixed as to reversely bias said diode in a non-selected mode, while a selected bit line and a selected word line are pulse driven in negative and positive directions, respectively, in data read and write modes.
4. The phase change memory device according to claim 1, wherein
said cell arrays are so stacked as to share bit lines and word lines with adjacent two cell arrays.
5. The phase change memory device according to claim 1, wherein
said first to third vertical wirings are contact plugs which are buried in an interlayer dielectric film surrounding said cell arrays.
6. The phase change memory device according to claim 1, wherein
neighboring two memory cells in each said cell array constitute a pair cell for storing complementary data one of which is a high resistance value state, and the other is a low resistance value state, and wherein
said complementary data of said pair cell are read out to a bit line pair as one bit of data.
7. The phase change memory device according to claim 6, wherein
said pair cell is selected such that another bit line is disposed between said bit line pair to which said complementary data are read out.
8. The phase change memory device according to claim 1, wherein
said readwrite circuit comprises:
a global bus region having a plurality of data lines to which read data are transferred and a plurality of write pulse signal lines for transferring write pulses to said bit lines, said data lines and said write pulse signal lines being so disposed as to cross a central portion of said cell layout region in said second direction;
first and second bit line select circuits disposed along said first and second boundaries of said cell layout region, respectively, to which the respective bit lines of neighboring two cell arrays are connected;
first and second sense amp arrays for sensing data of bit lines selected by said first and second bit line select circuits, respectively, said first and second sense amp arrays being disposed between said first, second bit line select circuits and said global bus region, respectively;
a word line select circuit disposed along one of said third and fourth boundaries of said cell layout region, to which shared word lines of said neighboring two cell arrays are connected; and
a write circuit disposed along the other of said third and fourth boundaries of said cell layout region for generating said write pulses supplied to said write pulse signal lines.
9. The phase change memory device according to claim 8, wherein
said shared word lines are simultaneously activated for a certain range which is selected by said word line select circuit, and the respective bit lines of said neighboring two cell arrays are simultaneously selected for the respective certain ranges which are selected by said first and second bit line select circuits, respectively, so that the respective plural memory cells in said neighboring two cell arrays are simultaneously accessed.
10. The phase change memory device according to claim 9, wherein
said first and second sense amp arrays have sense amps for simultaneously sensing data of the respective plural memory cells which are simultaneously selected in said neighboring two cell arrays, sensed data of which are simultaneously transferred to said data lines in said global bus region.
11. The phase change memory device according to claim 9, wherein
said write circuit is configured to simultaneously output write pulses, which are to be transferred to the respective plural bit lines simultaneously selected in said neighboring two cell arrays, to said write pulse signal lines in said global bus region.
12. The phase change memory device according to claim 8, wherein
neighboring two memory cells in each said cell array constitute a pair cell for storing complementary data, one of which is a high resistance value state and the other is a low resistance value state, and wherein
each of said first and second sense amp arrays comprises differential type current sensing amplifiers arranged therein, each of said current sensing amplifiers being connected to a bit line pair to which said pair cell is connected for sensing a current difference due to said complementary data.
13. The phase change memory device according to claim 8, wherein
said write circuit comprises:
a logic pulse generation circuit for generating positive logic pulses and negative logic pulses to be supplied to selected word lines and selected bit lines in each said cell array, respectively, said positive logic pulses and negative logic pulses being controlled to have overlap widths therebetween in correspondence with write data; and
a write pulse generation circuit for selectively boosting said negative logic pulses output from said logic pulse generation circuit in correspondence with write data to output said write pulse signal lines.
14. The phase change memory device according to claim 13, wherein
said logic pulse generation circuit comprises:
a pulse generation circuit for generating two pulses with the same pulse width, which are phase-shifted each other; and
a logic gate circuit for outputting said negative logic pulses and positive logic pulses with an overlap time determined by combination logics determined depending on write data.
15. The phase change memory device according to claim 1, wherein
said plurality of cell arrays comprise:
a first cell array having a plurality of mutually parallel first bit lines formed on an interlayer dielectric film covering said readwrite circuit, a plurality of memory cells laid out on each first bit line at a certain pitch, and a plurality of first word lines laid out on said memory cells in such a manner as to commonly connect together plural memory cells aligned in a direction crossing said first bit lines;
a second cell array being formed above said first cell array while sharing said first word lines with said first cell array and having a plurality of memory cells arrayed in the same layout as said first cell array and a plurality of second bit lines overlying the memory cells in such a manner as to commonly connect together plural memory cells aligned in a direction crossing said first word lines;
a third cell array being formed above said second cell array while sharing said second bit lines with said second cell array and having a plurality of memory cells laid out in the same layout as said second cell array and a plurality of second word lines overlying the memory cells in such a manner as to commonly connect together plural memory cells aligned in a direction crossing said second bit lines; and
a fourth cell array being formed above said third cell array while sharing said second word lines with said third cell array and having a plurality of memory cells disposed in the same layout as the memory cells of said third cell array and a plurality of third bit lines overlying the memory cells in such a manner as to commonly connect together plural memory cells aligned in a direction crossing said second word lines.
16. The phase change memory device according to claim 15, wherein
said memory cell of each said cell array has a chalcogenide and a diode which are stacked at each corresponding cross portion of said first to third bit lines and said first and second word lines.
17. The phase change memory device according to claim 16, wherein
the lamination order of said chalcogenide and diode is inverse between upper and lower neighboring cell arrays, and said diode is formed to have a polarity with the side of said first to third bit lines as a cathode.
18. The phase change memory device according to claim 15, wherein
said readwrite circuit comprises:
a global bus region having a plurality of data lines to which read data are transferred and a plurality of write pulse signal lines for transferring write pulses to said bit lines, said data lines and said write pulse signal lines being so disposed as to cross a central portion of said cell layout region in said second direction;
a first bit line select circuit disposed along said first boundary of said cell layout region, to which said first and third bit lines are commonly connected;
a second bit line select circuit disposed along said second boundary of said cell layout region, to which said second bit lines are connected;
first and second sense amp arrays for sensing data of bit lines selected by said first and second bit line select circuits, respectively, said first and second sense amp arrays being disposed between said first, second bit line select circuits and said global bus region, respectively;
a word line select circuit disposed along one of said third and fourth boundaries of said cell layout region, to which said first and second word lines are connected; and
a write circuit disposed along the other of said third and fourth boundaries of said cell layout region for generating said write pulses supplied to said write pulse signal lines.
19. The phase change memory device according to claim 18, wherein
said word line select circuit is configured to simultaneously activate a certain range of either one of said first and second word lines, and wherein
said first and second bit line select circuit are configured to simultaneously select a certain range of either one of said first and third bit lines, and simultaneously select a certain range of said second bit lines, respectively.
20. The phase change memory device according to claim 19, wherein
said first and second sense amp arrays have sense amps for simultaneously sensing data of the respective plural memory cells which are simultaneously selected in said first and second cell arrays or in said third and fourth cell arrays, sensed data of which are simultaneously transferred to said data lines in said global bus region.
21. The phase change memory device according to claim 19, wherein
said write circuit is configured to simultaneously output write pulses, which are to be transferred to the respective plural bit lines simultaneously selected in said first and second cell arrays or in said third and fourth cell arrays, to said write pulse signal lines in said global bus region.
22. The phase change memory device according to claim 15, wherein
neighboring two memory cells sharing said first or second word lines in each of said first to fourth cell arrays constitute a pair cell for storing complementary data one of which is a high resistance value state, and the other is a low resistance value state, and wherein
said complementary data of said pair cell are read out to a bit line pair as one bit of data.
23. The phase change memory device according to claim 22, wherein
said pair cell is selected such that another bit line is disposed between said bit line pair to which said complementary data are read out.

1. A human fatigue assessment device comprising:
a physiological signal measuring unit configured to measure a pulse wave signal of a user;
a feature value extracting unit configured to extract first feature values each of which is obtained from a systolic posterior component of the pulse wave signal measured by said physiological signal measuring unit;
a storage unit in which the first feature values extracted by said feature value extracting unit are stored; and
a fatigue determining unit configured to determine whether or not the user is fatigued, using the first feature values extracted by said feature value extracting unit,
wherein said fatigue determining unit is configured to compare a first feature value among the first feature values extracted by said feature value extracting unit and at least one of the first feature values stored in said storage unit, to determine whether or not the user is fatigued,
wherein said human fatigue assessment device further comprises
a checking unit configured to generate checking information for checking whether the user is in an open-eye state or in a closed-eye state,

wherein said physiological signal measuring unit is further configured to measure a brain signal of the user as a physiological signal, and to attach the checking information to the measured physiological signal,
wherein said feature value extracting unit is further configured to extract second feature values each of which (i) is obtained from the physiological signal measured by said physiological signal measuring unit and (ii) is related to at least one of (a) a power value in an \u03b1 waveband in a time period during which the checking information indicates that the user is in the closed-eye state and (b) a power value in a \u03b2 waveband in a time period during which the checking information indicates that the user is in the open-eve state or the closed-eye state,
wherein said storage unit stores the second feature values extracted by said feature value extracting unit, and
wherein said human fatigue assessment device further comprises
a fatigue type determining unit configured to determine, when said fatigue determining unit determines that the user is fatigued, a type of the fatigue of the user as to whether the fatigue is due to a first work or due to a second work that is more monotonous than the first work, by comparing a second feature value among the second feature values extracted by said feature value extracting unit and at least one of the second feature values stored in said storage unit.
2. The human fatigue assessment device according to claim 1,
wherein said feature value extracting unit is configured to calculate an accelerated plethysmogram from the pulse wave signal, and to extract the first feature values, using information on at least a c wave or a d wave which is a component wave of an accelerated plethysmogram corresponding to the systolic posterior component.
3. The human fatigue assessment device according to claim 2,
wherein said feature value extracting unit is configured to extract a ratio of a peak value of the c wave with respect to a peak value of an a wave, a b wave, or an e wave in the accelerated plethysmogram as the first feature value, and
wherein said fatigue determining unit is configured to determine that the user is fatigued, when absolute values of the first feature values increase in time-series.
4. The human fatigue assessment device according to claim 2,
wherein said feature value extracting unit is configured to extract a difference between peak values of the a wave and the c wave in the accelerated plethysmogram, and
wherein said fatigue determining unit is configured to determine that the user is fatigued when absolute values of the first feature values decrease in time-series.
5. The human fatigue assessment device according to claim 2,
wherein said feature value extracting unit is configured to extract a value obtained by dividing a difference between peak values of the c wave and the d wave in the accelerated plethysmogram by the a wave in the accelerated plethysmogram, and
wherein said fatigue determining unit is configured to determine that the user is fatigued when absolute values of the first feature values increase in time-series.
6. The human fatigue assessment device according to claim 1, further comprising
a device controller for controlling an external device which stimulates the user when said fatigue determining unit determines that the user is fatigued.
7. The human fatigue assessment device according to claim 1,
wherein when said feature value extracting unit extracts the second feature values as being related to a power value in the \u03b1 waveband in a time period during which the checking information indicates that the user is in the closed-eye state, said fatigue type determining unit is configured to determine that the fatigue is due to the first work when the second feature values increase in time-series.
8. The human fatigue assessment device according to claim 1,
wherein when said feature value extracting unit extracts the second feature values as being related to a power value in a \u03b2 waveband in a time period during which the checking information indicates that the user is in the open-eye state or the closed-eye state, said fatigue type determining unit is configured to determine that the fatigue is due to the second work when the second feature values decrease in time-series.
9. A human fatigue assessment method for assessing a fatigue of a living body by a computer, said method comprising:
measuring a pulse wave signal of a user;
extracting first feature values each of which is obtained from a systolic posterior component of the pulse wave signal measured in said measuring;
storing, in a storage unit, the first feature values extracted in said extracting; and
determining, using the computer, whether or not the user is fatigued, using the first feature values extracted in said extracting,
wherein, in said determining, a first feature value among the first feature values extracted in said extracting and at least one of the first feature values read from the storage unit among the first feature values stored in the storage unit are compared to determine whether or not the user is fatigued,
wherein said human fatigue assessment method further comprises
generating checking information for checking whether the user is in an open-eye state or in a closed-eye state,

wherein said measuring includes measuring a brain signal of the user as a physiological signal, and attaching the checking information to the measured physiological signal,
wherein said extracting includes extracting second feature values each of which (i) is obtained from the physiological signal and (ii) is related to at least one of (a) a power value in an \u03b1 waveband in a time period during which the checking information indicates that the user is in the closed-eye state and (b) a power value in a \u03b2 waveband in a time period during which the checking information indicates that the user is in the open-eye state or the closed-eye state,
wherein said human fatigue assessment method further comprises
storing, in the storage unit, the second feature values extracted in said extracting, and wherein said determining includes, when it is determined that the user is fatigued, determining a type of the fatigue of the user as to whether the fatigue is due to a first work or due to a second work that is more monotonous than the first work, by comparing a second feature value among the second feature values extracted in said extracting and at least one of the second feature values stored in the storage unit.
10. A program stored in a non-transitory computer readable recording medium, said program causing a computer to execute the human fatigue assessment method according to claim 9.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An optoelectronic device packaging assembly, comprising:
an electrical sub-mount including a mounting area and a sub-mount bonding pad;
a device turning mount having a sub-mount mounting side attached to the mounting area of the electrical sub-mount and a device mounting side having a device mounting area oriented in a plane substantially perpendicular to the mounting area of the electrical sub-mount;
a light-emitting device including a device bonding pad and one or more semiconductor layers terminating at a common light-emitting surface and operable to emit light from the light-emitting surface, wherein the light-emitting device is attached to the device mounting area of the device turning mount with the light-emitting surface oriented in a plane substantially parallel to the mounting area of the electrical sub-mount and the device bonding pad adjacent the sub-mount bonding pad; and
a direct electrical connection between the device bonding pad and the sub-mount bonding pad, wherein the electrical connection includes one or more electrically conductive bumps forming a continuous electrical connection from the device bonding pad to the sub-mount bonding pad.
2. The packaging assembly of claim 1, wherein the light-emitting surface of the light-emitting device is oriented to emit light away from the electrical sub-mount.
3. The packaging assembly of claim 1, wherein the light-emitting surface of the light-emitting device is oriented to emit light toward the electrical sub-mount.
4. An optoelectronic device packaging assembly, comprising:
an electrical sub-mount including a mounting area;
a device turning mount having a sub-mount mounting side attached to the mounting area of the electrical sub-mount and a device mounting side having a device mounting area oriented in a plane substantially perpendicular to the mounting area of the electrical sub-mount, wherein the device turning mount includes an electrical trace having a sub-mount bonding portion oriented in a plane substantially parallel to the mounting area of the electrical sub-mount and a device bonding portion oriented in a plane substantially perpendicular to the mounting area of the electrical sub-mount; and
a light-emitting device including one or more semiconductor layers terminating at a common light-emitting surface and operable to emit light from the light-emitting surface, wherein the light-emitting device is attached to the device mounting area of the device turning mount with the light-emitting surface oriented in a plane substantially parallel to the mounting area of the electrical sub-mount.
5. The packaging assembly of claim 4, wherein the electrical trace extends through a volume of the device turning mount.
6. The packaging assembly of claim 4, wherein the device bonding portion of the electrical trace corresponds to electrically conducting material formed in a groove defined in a surface of the device mounting side of the device turning mount.
7. The packaging assembly of claim 4, further comprising a wire bond connected between the electrical sub-mount and the sub-mount bonding portion of the electrical trace and a wire bond connected between the device bonding portion of the electrical trace and the light-emitting device.
8. The packaging assembly of claim 1, wherein one of the electrically conductive bumps is a solder bump directly bonded to the sub-mount bonding pad.
9. The packaging assembly of claim 8, wherein the one or more electrically conductive bumps include a second solder bump directly bonded to the device bonding pad and directly bonded to the first solder bump.
10. The packaging assembly of claim 8, wherein the one or more electrically conductive bumps include a wire stud bump directly bonded to the device bonding pad and directly bonded to the solder bump.
11. The packaging assembly of claim 1, wherein the one or more electrically conductive bumps correspond to a continuous solder mass electrically directly connecting the device bonding pad to the sub-mount bonding pad.
12. The packaging assembly of claim 1, wherein the electrical sub-mount is formed of silicon.
13. The packaging assembly of claim 1, wherein the device turning mount is electrically insulating.
14. The packaging assembly of claim 1, wherein the electrical sub-mount comprises multiple sub-mount bonding pads, and further comprising:
one or more additional light-emitting devices each including a respective device bonding pads and one or more semiconductor layers terminating at a common light-emitting surface and operable to emit light from the light-emitting surface, wherein each light-emitting device is attached to the device mounting area of the device turning mount with a respective light-emitting surface oriented in a plane substantially parallel to the mounting area of the electrical sub-mount and the respective device bonding pad adjacent a corresponding one of the sub-mount bonding pads; and
direct electrical connections between the device bonding pads and respective ones of the corresponding sub-mount bonding pads, wherein each of the electrical connections includes one or more electrically conductive bumps forming a continuous electrical connection from a respective one of the device bonding pads to the corresponding sub-mount bonding pad.
15. The packaging assembly of claim 1, further comprising a housing formed of silicon, attached to the electrical sub-mount, and enclosing the device turning mount and the light-emitting device.
16. The packaging assembly of claim 1, wherein the light-emitting device is an edge-emitting laser.
17. An optoelectronic device packaging assembly, comprising:
an electrical sub-mount including a mounting area;
a device turning mount having a sub-mount mounting side attached to the mounting area of the electrical sub-mount and a device mounting side having a device mounting area oriented in a plane substantially perpendicular to the mounting area of the electrical sub-mount; and
an array of edge-emitting lasers attached to the device mounting area of the device turning mount with each edge-emitting laser oriented to emit light in a direction substantially perpendicular to the electrical sub-mount, each edge-emitting laser being electrically connected to the electrical sub-mount by a direct electrical connection between a respective laser bonding pad and a corresponding bonding pad of the electrical sub-mount.
18. The packaging assembly of claim 17, wherein each electrical connection includes a wire, one end of each wire being wire bonded to a respective laser bonding pad and another end of each wire being wire bonded to a respective electrical sub-mount bonding pad.
19. The packaging assembly of claim 18, wherein one end of each wire is stud bump bonded to a respective laser bonding pad and another end of each wire is wire bonded to a respective electrical sub-mount bonding pad.
20. The packaging assembly of claim 18, wherein each electrical connection includes a solder bump bonded to a respective electrical sub-mount bonding pad.
21. The packaging assembly of claim 20, wherein each electrical connection includes a second solder bump bonded to a respective laser bonding pad and to a solder ball bonded to a respective electrical sub-mount bonding pad.
22. The packaging assembly of claim 20, wherein each electrical connection includes a wire stud bump electrically coupled between a respective laser bonding pad and a solder ball bonded to a respective electrical sub-mount bonding pad.
23. The packaging assembly of claim 18, wherein each electrical connection corresponds to a solder mass electrically connecting a respective laser bonding pad to a respective electrical sub-mount bonding pad.
24. The packaging assembly of claim 1, wherein the electrical sub-mount is formed of silicon.
25. The packaging assembly of claim 4, wherein the device turning mount is electrically insulating.
26. The packaging assembly of claim 25, wherein the device turning mount comprises two electrically insulating substrates.