Author: claimsbot

1. A liquid crystal display screen, comprising:
an upper board comprising a touch panel;
the touch panel comprises a plurality of transparent electrodes, at least one of the plurality of transparent electrodes comprises a transparent carbon nanotube structure,
the transparent carbon nanotube structure comprising a plurality of metallic carbon nanotubes;

a lower board comprising a thin film transistor panel; and
a liquid crystal layer located between the upper board and the lower board.
2. The liquid crystal display screen of claim 1, wherein the carbon nanotube structure comprises one or more carbon nanotube films.
3. The liquid crystal display screen of claim 2, wherein the carbon nanotube structure has a thickness of about 0.5 nm to about 100 \u03bcm.
4. The liquid crystal display screen of claim 2, wherein the carbon nanotube films are adjacent to each other or stacked on each other.
5. The liquid crystal display screen of claim 2, wherein the carbon nanotube film comprises a disordered carbon nanotube film.
6. The liquid crystal display screen of claim 5, wherein the carbon nanotubes of the disordered carbon nanotube film are entangled with each other.
7. The liquid crystal display screen of claim 2, wherein the carbon nanotube film comprises an ordered carbon nanotube film.
8. The liquid crystal display screen of claim 7, wherein the ordered carbon nanotube film comprises a plurality of carbon nanotubes joined end to end via van der Waals.
9. The liquid crystal display screen of claim 1, wherein the carbon nanotube structure comprises at least two carbon nanotube films stacked on each other, an angle is formed between the carbon nanotubes of two adjacent carbon nanotube films, the angle is in the range about 0 degree to about 90 degrees.
10. The liquid crystal display screen of claim 1, wherein the carbon nanotubes of the carbon nanotube structure are selected from the group consisting of single walled carbon nanotubes, double walled carbon nanotubes, and multi walled carbon nanotubes, the single walled carbon nanotubes have diameters of about 0.5 nm to about 50 nm, the double walled carbon nanotubes have diameters of about 1.0 nm to about 50 nm, the multi walled carbon nanotubes have diameters of about 1.5 \u03bcm to about 50 nm.
11. The liquid crystal display screen of claim 1, wherein the carbon nanotube structure is a composite layer comprising at least one carbon nanotube film and a polymer material infiltrated in the carbon nanotube film.
12. The liquid crystal display screen of claim 11, wherein the polymer comprises of a material that is selected from the group consisting of polycarbonate (PC), polymethyl methacrylate acrylic (PMMA), polyethylene terephthalate (PET), benzocyclobutenes (BCB), polystyrene, polyethylene, polycarbonate, and polycycloolefins.
13. The liquid crystal display screen of claim 1, wherein the transparent electrodes comprises of a plurality of first transparent electrodes and a plurality of second transparent electrodes, the touch panel further comprises:
a first electrode plate comprising:
a first substrate, the plurality of first transparent electrodes spaced from each other and disposed on the first substrate and aligned along a first direction, and
a plurality of first signal wires, each of the first transparent electrodes is connected to one of the first transparent electrodes;

a second electrode plate, spaced from the first electrode plate comprising:
a second substrate, the plurality of second transparent electrodes spaced from each other, and disposed on the second substrate and aligned along a second direction; and
a plurality of second signal wires, and each of the second transparent electrodes is connected to one of the second transparent electrodes;
an insulating layer disposed the periphery of the second electrode plate and interposed between the first electrode plate and the second electrode plate; and
a plurality of dot spacers disposed between the first electrode plate and the second electrode plate.
14. The liquid crystal display screen of claim 13, wherein the first transparent electrodes are aligned along a first direction, the second transparent electrodes are aligned along a second direction, and the first direction is perpendicular to the second direction.
15. The liquid display screen of claim 13, wherein each of the first transparent electrodes and the second transparent electrodes are made of metallic carbon nanotubes.
16. The liquid crystal display screen of claim 13, wherein the plurality of the first transparent electrodes and the plurality of the second transparent electrodes are uniformly arranged, the first and second transparent electrodes have strip-shaped structures and have width of about 20 \u03bcm to about 250 \u03bcm, the first and second transparent electrodes have thickness of about 0.5 nm to about 100 \u03bcm, the first and second transparent electrodes have a distance therebetween of about 20 \u03bcm to about 50 \u03bcm.
17. The liquid crystal display screen of claim 13, wherein the plurality of the first transparent electrodes each has a first end and a second end, the first end is electrically connected to the X-coordinates driving source via the first signal wire, the second end is electrically connected to a sensor via the first signal wire; the plurality of the second transparent electrodes each has a first end and a second end, the first end of the second transparent electrodes is electrically connected to the Y-coordinates driving source via the second signal wire, the second end of the second transparent electrodes is grounded.
18. The liquid crystal display screen of claim 13, wherein the plurality of the first signal wires are parallel to each other, the plurality of the second signal wires are parallel to each other, the first and second signal wires comprise of a material selected from a group consisting of indium tin oxide, antimony tin oxide, conductive resin, carbon nanotubes, and combinations thereof.
19. The liquid crystal display screen of claim 1, wherein the upper board further comprises a first polarizing layer and a first alignment layer, the first polarizing layer is disposed directly on a lower surface of the second substrate of the touch panel, the first alignment layer is disposed on a lower surface of the first polarizing layer.
20. The liquid crystal display screen of claim 18, wherein the first polarizing layer comprises a plurality of carbon nanotubes arranged along a preferred orientation.
21. The liquid crystal display screen of claim 18, wherein the first polarizing layer has a thickness of about 1 \u03bcm to about 0.5 mm.
22. The liquid crystal display screen of claim 1, wherein the thin film transistor panel further comprises:
a third substrate;
a display driving circuit;
a plurality of thin film transistors disposed the third substrate and electrically connected to the display driving circuit; and
a plurality of pixel electrodes, one of pixel electrodes being electrically connected to each of the thin film transistors.
23. The liquid crystal display screen of claim 1, wherein the lower board further comprises a second alignment layer and a second polarizing layer, the second polarizing layer is disposed on a lower surface of the thin film transistor panel, the second alignment layer is disposed on an upper surface of the thin film transistor panel and adjacent to the liquid crystal layer.
24. The liquid crystal display screen of claim 1, wherein the lower board further comprises a carbon nanotube layer configured for both polarizing light and aligning liquid crystals, wherein the carbon nanotube layer comprises a plurality of carbon nanotubes substantially arranged along a primary direction.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method comprising:
establishing a trajectory through the skull into the brain to a target,
drilling a hole in the skull using a drill,
verifying the trajectory of the drilled hole during drilling using image guidance provided by a probe received by the drill, and
placing an access member in the drilled hole using the drill,
verifying the trajectory of the access member during placement using a probe received by the drill.
2. The method of claim 1 wherein the drill defines a lumen.
3. The method of claim 2 wherein the probe is received in the lumen defined by the drill.
4. The method of claim 1, further comprising placing a medical device in a lumen defined by the access member.
5. The method of claim 4, further comprising securing the medical device in the access member.
6. The method of claim 4, wherein the medical device is selected from a group consisting of a ventriculostomy catheter, convention therapy catheter, epilepsy depth electrode, thermocoagulation probe, lesioning probe, stereotactic needle and ablative probe.
7. The method of claim 1, wherein the probe is tracked by navigation software.
8. The method of claim 7, wherein said navigation software tracks the probe relative to images of a patient’s body.

1. A method of providing at least one electrical conductor to a wellhead containing a fluid while preventing fluid leakage from the wellhead, the method comprising:
providing a cylindrical housing having a through hole, the housing adapted to be mounted to the wellhead;
passing at least one electrical conductor through the hole of the cylindrical housing; and
sealing the through hole and the at least one electrical conductor to substantially prevent the passage of the fluid through the housing.
2. The method as recited in claim 1, wherein the fluid comprises at least one of a gas and a liquid.
3. The method as recited in claim 1, wherein the housing is adapted to be mounted to the wellhead comprises a housing having an external thread engagable with the wellhead.
4. The method as recited in claim 1, wherein passing at least one electrical conductor comprises passing at least one single, solid wire electrical conductor through the hole.
5. The method as recited in claim 1, wherein sealing the through hole and the at least one electrical conductor comprises providing a hardenable fluid to the through hole and hardening the hardenable fluid to provide a substantially fluid-tight seal between an inside surface of the through hole and an outside surface of the at least one electrical conductor.
6. The method as recited in claim 1, wherein the at least one electrical conductor comprises at least one coated single-solid-wire electrical conductor.
7. The method as recited in claim 1, wherein passing at least one electrical conductor through the hole of the connector comprises passing at least one electrical conductor comprising an electrical coupling.
8. The method as recited in claim 7, wherein the electrical coupling comprises a first male connector and a second female connector.
9. An apparatus for providing at least one electrical conductor to a wellhead containing a fluid while preventing fluid leakage from the wellhead, the apparatus comprising:
a cylindrical housing having a through hole, the housing adapted to be mounted to the wellhead;
at least one electrical conductor passing through the hole of the cylindrical housing; and
means for sealing the through hole and the at least one electrical conductor to substantially prevent the passage of the fluid through the housing.
10. The apparatus as recited in claim 9, wherein the fluid comprises at least one of a gas and a liquid.
11. The apparatus as recited in claim 9, wherein the housing adapted to be mounted to the wellhead comprises a housing having an external thread adapted to engage the wellhead.
12. The apparatus as recited in claim 9, wherein the at least one electrical conductor comprises at least one single-solid-wire electrical conductor.
13. The apparatus as recited in claim 9, wherein the means for sealing the through hole and the at least one electrical conductor comprises a hardenable fluid adapted to provide a substantially fluid-tight seal between an inside surface of the through hole and an outside surface of the at least one electrical conductor when hardened.
14. The apparatus as recited in claim 9, wherein the at least one electrical conductor comprises at least one coated, single-solid-wire electrical conductor.
15. The apparatus as recited in claim 9, wherein the at least one electrical conductor comprises an electrical coupling.
16. The apparatus as recited in claim 15, wherein the electrical coupling comprises a first male connector and a second female connector.
17. An electrical coupling assembly adapted to provide at least one electrical conductor to a wellhead containing a fluid while preventing fluid leakage from the wellhead, the coupling assembly comprising:
a cylindrical housing having a through hole, the housing adapted to be mounted to the wellhead;
a first electrical connector mounted in the housing and having at least one first electrical conductor;
a second electrical connector adapted to engage the first electrical connector and having at least one second electrical conductor; and
means for sealing the through hole about at least one of the first electrical connector and the at least one electrical connector to substantially prevent the passage of the fluid through the housing.
18. The coupling as recited in claim 17, wherein at least one of the first electrical connector and the second electrical connector comprise a plurality of electrodes.
19. The coupling as recited in claim 17, wherein the means for sealing the through hole comprises at least one hardenable fluid.
20. The coupling as recited in claim 19, wherein the hardenable fluid comprises at least one of an adhesive, an epoxy, and a silicone.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A semiconductor device, comprising:
a semiconductor layer formed by epitaxial growth in a first region which is obtained by etching a semiconductor substrate to a predetermined depth, a surface of the semiconductor layer having a same height from the bottom of the semiconductor substrate as a height of a surface of the semiconductor substrate;
a buried insulating layer buried between the semiconductor substrate and the semiconductor layer; and
an element isolation region separating each element region in the semiconductor layer and isolating the semiconductor layer from the semiconductor substrate in plan.
2. A method of manufacturing a semiconductor device on a semiconductor substrate that has a first element region having a silicon-on-insulator structure (SOI) structure, a second element region having a bulk structure and an element isolation region separating each region, the first region and the second region being provided in a plural number, the method comprising:
etching a part of a first area situated next to the first element region in the first element region andor the element isolation region on the semiconductor substrate to a predetermined depth;
forming a mask layer in an unetched second area other than the etched first area;
forming a first semiconductor layer made of an material that has a larger etching rate than an etching rate of the semiconductor substrate selectively in an unmasked area;
forming a second semiconductor layer made of an material that has a smaller etching rate than the etching rate of the first semiconductor layer on the first semiconductor layer;
forming a first groove in an third area where the first semiconductor layer and the second semiconductor layer are formed in the element isolation region, the first groove penetrating the first semiconductor layer and the second semiconductor layer and exposing the semiconductor substrate;
forming a supporting layer in the first groove and in at least a part of the first element region, the supporting layer supporting the second semiconductor layer on the semiconductor substrate;
forming a second groove in the element isolation region except an area where the first groove is formed, the second groove exposing the first semiconductor layer;
forming a cavity under the second semiconductor layer by removing the first semiconductor layer by etching the first semiconductor layer through the second groove; and
forming a buried insulating layer embedded in the cavity through the second groove.
3. The method of manufacturing a semiconductor device according to claim 2, wherein the semiconductor substrate is exposed at the bottom of the second groove when the second groove is formed.
4. The method of manufacturing a semiconductor device according to claim 2, wherein a third groove is simultaneously formed in the element isolation region that separates each region in the second element region when the second groove exposing the first semiconductor layer is formed.
5. The method of manufacturing a semiconductor device according to claim 2, wherein the semiconductor substrate is etched to a depth substantially same as a sum of thicknesses of the first semiconductor layer and the second semiconductor layer when the part of the first area is etched.
6. The method of manufacturing a semiconductor device according to claim 2, wherein the semiconductor substrate is a single-crystalline semiconductor substrate, and the first semiconductor layer and the second semiconductor layer is a single-crystalline semiconductor layer formed by epitaxial growth.
7. The method of manufacturing a semiconductor device according to claim 2, wherein the semiconductor substrate and the second semiconductor layer are made of single-crystalline silicon, and the first semiconductor layer is made of a single-crystalline silicon germanium.
8. The method of manufacturing a semiconductor device according to claim 2 wherein an insulating film is formed on the second semiconductor layer before the first groove is formed.
9. The method of manufacturing a semiconductor device according to claim 8, wherein the insulating layer includes at least a silicon nitride film.
10. A method of manufacturing a semiconductor device on a semiconductor substrate that has a first element region having a silicon-on-insulator structure (SOI) structure, a second element region having a bulk structure and an element isolation region separating each element region, the first region and the second region being provided in a plural number, the method comprising:
forming a mask in the second element region on the semiconductor substrate;
etching a part of a first area situated next to the first element region in the first element region andor the element isolation region to a predetermined depth;
forming a first semiconductor layer made of an material that has a larger etching rate than an etching rate of the semiconductor substrate on the semiconductor substrate and the mask;
forming a second semiconductor layer made of an material that has a smaller etching rate than the etching rate of the first semiconductor layer on the first semiconductor layer;
removing the first semiconductor layer and the second semiconductor layer that exit in an unetched area;
forming a first groove in an second area where the first semiconductor layer and the second semiconductor layer are formed in the element isolation region, the first groove penetrating the first semiconductor layer and the second semiconductor layer and exposing the semiconductor substrate;
forming a supporting layer in the first groove and in at least a part of the first element region, the supporting layer supporting the second semiconductor layer on the semiconductor substrate;
forming a second groove in the element isolation region except an area where the first groove is formed, the second groove exposing the first semiconductor layer;
forming a cavity under the second semiconductor layer by removing the first semiconductor layer by etching the first semiconductor layer through the second groove; and
forming a buried insulating layer embedded in the cavity through the second groove.
11. The method of manufacturing a semiconductor device according to claim 10, wherein the semiconductor substrate is exposed at the bottom of the second groove when the second groove is formed.
12. The method of manufacturing a semiconductor device according to claim 10, wherein a third groove is simultaneously formed in the element isolation region that separates each region in the second element region when the second groove exposing the first semiconductor layer is formed.
13. The method of manufacturing a semiconductor device according to claim 10, wherein the semiconductor substrate is etched to a depth substantially same as a sum of thicknesses of the first semiconductor layer and the second semiconductor layer when the part of the first area is etched.
14. The method of manufacturing a semiconductor device according to claim 10, wherein the semiconductor substrate is a single-crystalline semiconductor substrate, and the first semiconductor layer and the second semiconductor layer is a single-crystalline semiconductor layer formed by epitaxial growth.
15. The method of manufacturing a semiconductor device according to claim 10, wherein the semiconductor substrate and the second semiconductor layer are made of single-crystalline silicon, and the first semiconductor layer is made of a single-crystalline silicon germanium.
16. The method of manufacturing a semiconductor device according to claim 10, wherein an insulating film is formed on the second semiconductor layer before the first groove is formed.
17. The method of manufacturing a semiconductor device according to claim 16, wherein the insulating layer includes at least a silicon nitride film.