Author: claimsbot

1. A light-emitting diode device having two electrode pads for connecting to an external power, comprising:
a substrate;
a plurality of light-emitting diode units on the substrate; and
a plurality of conductive connecting structures electrically connecting the plurality of light-emitting diode units;
wherein the two electrode pads are encircled by the plurality of light-emitting diode units.
2. The light-emitting diode device of claim 1, wherein each of the plurality of light-emitting diode units comprises a first conductive type semiconductor layer on the substrate; a second conductive type semiconductor layer on the first conductive type semiconductor layer; and a light-emitting layer arranged between the first conductive type semiconductor layer and the second conductive type semiconductor layer.
3. The light-emitting diode device of claim 2, wherein each of the light-emitting diode units further comprises a first electrode formed on the first conductive type semiconductor layer and a second electrode formed on the second conductive type semiconductor layer.
4. The light-emitting diode device of claim 1, wherein the plurality of light-emitting diode units are spaced apart from each other with a distance larger than 35 \u03bcm.
5. The light-emitting diode device of claim 1, further comprising an adhesive layer formed between the substrate and the plurality of light-emitting diode units
6. The light-emitting diode device of claim 5, wherein the adhesive layer is a transparent adhesive layer.
7. The light-emitting diode device of claim 6, wherein the material of the transparent adhesive layer comprises a polymer material.
8. The light-emitting diode device of claim 6, wherein the material of the transparent adhesive layer comprises metal oxide.
9. The light-emitting diode device of claim 6, wherein the material of the transparent adhesive layer comprises inorganic material.
10. The light-emitting diode device of claim 1, wherein the substrate is a transparent substrate.
11. The light-emitting diode device of claim 1, wherein the substrate is a multi-layered substrate.
12. The light-emitting diode device of claim 2, wherein each of the conductive connecting structures is arranged between two adjacent light-emitting diode units and electrically connect the first conductive type semiconductor layer of one of two adjacent light-emitting diode units to the second conductive type semiconductor layer of the other of the two adjacent light-emitting diode units.
13. The light-emitting diode device of claim 1, wherein one of the plurality of light-emitting diode units is spaced apart from an edge of the substrate with a shortest distance not smaller than 20 \u03bcm.
14. The light-emitting diode device of claim 1, wherein the substrate comprises a first side and a second side, a total number of the plurality of light-emitting diode units formed along the first side is equal to a total number of the plurality of light-emitting diode units formed along the second side.
15. The light-emitting diode device of claim 1, further comprising one light-emitting diode unit encircled by the plurality of light-emitting diode units.
16. The light-emitting diode device of claim 1, wherein the plurality of light-emitting diode units is substantially arranged in a lattice form.
17. The light-emitting diode device of claim 12, wherein each of the plurality of light-emitting diode units comprises a longer side and a shorter side, and one of the conductive connecting structures is arranged between the shorter sides of the two adjacent light-emitting diode units.
18. The light-emitting diode device of claim 17, wherein the longer side of one of the plurality of light-emitting diode units is perpendicular to the longer side of another one of the plurality of light-emitting diode units.
19. The light-emitting diode device of claim 12, further comprising an insulating layer partially formed on the plurality of light-emitting diode units and between two adjacent light-emitting diode units.
20. The light-emitting diode device of claim 1, each of the plurality of light-emitting diode units comprises a growth substrate.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

What is claimed is:

1. A clock generator comprising:
a resistor;
a MOSFET having a gate, a drain and a source connected to said resistor for generating a reference current;
a first reference voltage independent on VDD and temperature for controlling said MOSFET;
a current mirror circuit for generating a first and a second mirror current by mirroring said reference current;
a first capacitor receiving said first mirror current and generating a first charged voltage;
a second capacitor receiving said second mirror current and generating a second charged voltage;
a second reference voltage generated from an input supply voltage for controlling said first and second charged voltage; and
a logic circuit receiving said first and second charged voltage and generating a clock signal.
2. The clock generator as set forth in claim 1, wherein said first capacitor, second capacitor and resistor determine the period of said clock signal.
3. A clock generator comprising:
a current mirror circuit for generating a first and a second mirror current by mirroring a reference current, which increases with temperature; and
a first capacitor receiving the first mirror current and generating a first charged voltage;
a second capacitor receiving the second mirror current and generating a second charged voltage; and
a logic circuit receiving the first and second charged voltages and generating a clock signal.
4. The clock generator as set forth in claim 3, and further comprising;
a resistor; and
a MOSFET having a gate, a drain and a source, the MOSFET being connected to the resistor for generating the reference current.
5. The clock generator as set forth in claim 4, wherein the MOSFET has a threshold voltage (Vt) that decreases with increasing temperature.
6. The clock generator as set forth in claim 5, wherein the threshold voltage (Vt) decreases with increasing temperature so that a current through the MOSFET increases with increasing temperature.
7. The clock generator as set forth in claim 6, wherein the threshold voltage (Vt) decreases with increasing temperature so that a frequency of the clock signal increases with increasing temperature.
8. The clock generator as set forth in claim 4, wherein the first capacitor, second capacitor and resistor determine the period of the clock signal.
9. The clock generator as set forth in claim 4, and further comprising a first reference voltage independent on VDD and temperature for controlling the MOSFET.
10. The clock generator as set forth in claim 7, and further comprising a second reference voltage generated from an input supply voltage for controlling the first and second charged voltage.
11. A method of generating a clock signal in a charge pump, comprising:
mirroring a reference current, which increases with temperature, to generate a first and a second mirror current;
receiving the first mirror current and generating a first charged voltage with a first capacitor;
receiving the second mirror current and generating a second charged voltage with a second capacitor; and
receiving the first and second charged voltages into a logic circuit and generating a clock signal.
12. The method as set forth in claim 11, wherein the mirroring of a reference current is preceded by generating the reference current using a MOSFET connected to a resistor, wherein a threshold voltage (Vt) of the MOSFET decreases with increasing temperature.
13. The method as set forth in claim 12, wherein the threshold voltage (Vt) decreases with increasing temperature so that a current through the MOSFET increases with increasing temperature.
14. The method as set forth in claim 13, wherein the threshold voltage (Vt) decreases with increasing temperature so that a frequency of the clock signal increases with increasing temperature.
15. The method as set forth in claim 12, and further comprising controlling the MOSFET with a first reference voltage independent of a supply voltage VDD and temperature.

1. A wireless transmitreceive unit (WTRU) comprising:
a transceiver configured to communicate on a primary cell and a secondary cell;
the transceiver is further configured to receive a medium access control (MAC) message indicating activation or deactivation of the secondary cell;
wherein on a condition that the MAC message indicates that the secondary cell is activated, the WTRU monitors the secondary cell for control messages;
wherein on a condition that the MAC message indicates that the secondary cell is deactivated, the WTRU ceases monitoring the secondary cell;
a processor configured to start a timer in response to the activation of the secondary cell; and
wherein on a condition that the timer expires, the WTRU deactivates the secondary cell.
2. The WTRU of claim 1 further comprising:
the transceiver is further configured to receive radio resource control signaling from a base station configuring the secondary cell.
3. The WTRU of claim 1, wherein the MAC message includes a bit map and a bit in the bit map indicates whether at least one of plurality of secondary cells is activated or deactivated.
4. The WTRU of claim 1, wherein the timer has a duration of a plurality of transmission time intervals.
5. The WTRU of claim 1, wherein the primary cell and the secondary cell are one of LTE or LTE-A cells.
6. The WTRU of claim 1, wherein the primary cell and the secondary cell are W-CDMA cells.
7. The WTRU of claim 1, wherein the WTRU only transmits a physical control channel using the primary cell.
8. A method performed by a wireless transmitreceive unit (WTRU), the method comprising:
communicating, by a transceiver of the WTRU, on a primary cell and a secondary cell;
receiving, by the transceiver, a medium access control (MAC) message indicating activation or deactivation of the secondary cell;
wherein on a condition that the MAC message indicates that the secondary cell is activated, the WTRU monitors the secondary cell for control messages;
wherein on a condition that the MAC message indicates that the secondary cell is deactivated, the WTRU ceases monitoring the secondary cell;
starting, by a processor of the WTRU, a timer in response to the activation of the secondary cell; and
wherein on a condition that the timer expires, the WTRU deactivates the secondary cell.
9. The method of claim 8 further comprising:
receiving, by the transceiver, radio resource control signaling from a base station configuring the secondary cell.
10. The method of claim 8, wherein the MAC message includes a bit map and a bit in the bit map indicates whether at least one of plurality of secondary cells is activated or deactivated.
11. The method of claim 8, wherein the timer has a duration of a plurality of transmission time intervals.
12. The method of claim 8, wherein the primary cell and the secondary cell are one of LTE or LTE-A cells.
13. The method of claim 8, wherein the primary cell and the secondary cell are W-CDMA cells.
14. The method of claim 8, wherein the WTRU only transmits a physical control channel using the primary cell.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of inserting implicit sequence points into computer program code to support debug operations, the method comprising:
performing, using a processor, optimization of the computer program code during compilation of the computer program code and, during the optimization, inserting implicit sequence points into the computer program code, wherein the implicit sequence points are configured to provide virtual reads of symbols contained in the computer program code when the implicit sequence points are reached during execution of the computer program code during a debug operation performed on the computer program code after the computer program code is optimized and compiled, wherein a view of a user program remains valid by constraining the optimization using implicitly generated virtual reads of user visible symbols at the implicit sequence points and wherein, when a debugger stops at at least one of the sequence points, user visible symbols hold respective values in a same manner the user visible symbols would hold the respective values without optimization being performed on the computer program code; and
configuring the computer program code to enable user modification of at least one respective value of at least one symbol when the debug operation is performed on the computer program code.
2. The method of claim 1, further comprising:
during the compilation of the computer program code, automatically determining locations in the computer program code where a user would want the implicit sequence points to be inserted into the computer program code based on a user experience provided by the computer program code, wherein inserting the implicit sequence points into the computer program code comprises inserting the implicit sequence points at the automatically determined locations.
3. The method of claim 1, wherein the implicit sequence points further provide virtual reads of indirect operations performed by the computer program code during execution of the computer program code, the indirect operations pertaining to operations that process at least one variable not specifically assigned in the computer program code.
4. The method of claim 1, wherein performing optimization of the computer program code comprises performing at least one level of optimization, the level of optimization selected from a group consisting of optimizing the computer program code to reduce an amount of time required to execute the computer program code and optimizing the computer program code to reduce an amount of memory utilized by the computer program code during operation.
5. The method of claim 1, wherein the implicit sequence points indicate points in the computer program code where execution is to be stopped, at least temporarily, during the debug operation.
6. The method of claim 1, wherein a number of the implicit sequence points inserted into the computer program code is a selected value within a predetermined range of values.
7. The method of claim 1, further comprising:
specifying a plurality of locations where the implicit sequence points are to be inserted into the computer program code in response to a user input received via a compiler configured to compile the computer program code;
wherein inserting implicit sequence points into the computer program code comprises inserting the implicit sequence points at the plurality of locations.
8. A method of inserting implicit sequence points into computer program code to support debug operations, the method comprising:
performing, using a processor, optimization of the computer program code during compilation of the computer program code and, during the optimization, inserting implicit sequence points into the computer program code, wherein the implicit sequence points are configured to provide virtual reads of symbols contained in the computer program code when the implicit sequence points are reached during execution of the computer program code during a debug operation performed on the computer program code after the computer program code is optimized and compiled, wherein a number of the implicit sequence points inserted into the computer program code is a selected value within a predetermined range of values in which a user is presented the predetermined range of values and prompted to select one of the values within the predetermined range.